From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
To: <bhelgaas@google.com>, <paul.gortmaker@windriver.com>,
<robh@kernel.org>, <colin.king@canonical.com>,
<linux-pci@vger.kernel.org>, <marc.zyngier@arm.com>
Cc: arnd@arndb.de, michal.simek@xilinx.com,
linux-kernel@vger.kernel.org,
Bharat Kumar Gogada <bharatku@xilinx.com>,
rgummal@xilinx.com, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/4] PCI: Xilinx NWL: Modifying flow handler for legacy interrupts
Date: Sat, 21 Jan 2017 16:41:11 +0530 [thread overview]
Message-ID: <1484997072-19276-3-git-send-email-bharatku@xilinx.com> (raw)
In-Reply-To: <1484997072-19276-1-git-send-email-bharatku@xilinx.com>
Legacy interrupts are level sensitive, so using handle_level_irq
is more approprate as it is masks interrupts until End point handles
interrupts and unmasks interrutps after End point handler is executed.
Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
---
drivers/pci/host/pcie-xilinx-nwl.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c
index e1809f9..50f9c0d 100644
--- a/drivers/pci/host/pcie-xilinx-nwl.c
+++ b/drivers/pci/host/pcie-xilinx-nwl.c
@@ -433,7 +433,7 @@ static void nwl_unmask_leg_irq(struct irq_data *data)
static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq,
irq_hw_number_t hwirq)
{
- irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_simple_irq);
+ irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq);
irq_set_chip_data(irq, domain->host_data);
return 0;
--
1.7.1
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next prev parent reply other threads:[~2017-01-21 11:11 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-21 11:11 [PATCH 1/4] PCI: Xilinx NWL: Fix, do not check for legacy status in while loop Bharat Kumar Gogada
2017-01-21 11:11 ` [PATCH 2/4] PCI: Xilinx NWL: Modifying irq chip for legacy interrupts Bharat Kumar Gogada
2017-01-23 18:37 ` Marc Zyngier
2017-01-24 10:19 ` Bharat Kumar Gogada
2017-01-21 11:11 ` Bharat Kumar Gogada [this message]
2017-01-23 18:38 ` [PATCH 3/4] PCI: Xilinx NWL: Modifying flow handler " Marc Zyngier
2017-01-24 10:25 ` Bharat Kumar Gogada
2017-01-21 11:11 ` [PATCH 4/4] PCI: Xilinx NWL: Fix, proc interrupts for legacy virtual irq shown as edge Bharat Kumar Gogada
2017-01-23 18:23 ` [PATCH 1/4] PCI: Xilinx NWL: Fix, do not check for legacy status in while loop Marc Zyngier
2017-01-24 10:15 ` Bharat Kumar Gogada
2017-01-24 11:07 ` Marc Zyngier
2017-01-24 14:00 ` Bharat Kumar Gogada
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