* [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers
@ 2017-07-06 6:33 Zhiqiang Hou
2017-07-06 6:33 ` [PATCH 2/3] PCI: designware: enable write permission before updating class code Zhiqiang Hou
` (2 more replies)
0 siblings, 3 replies; 13+ messages in thread
From: Zhiqiang Hou @ 2017-07-06 6:33 UTC (permalink / raw)
To: linux-pci, bhelgaas, jingoohan1, Joao.Pinto; +Cc: Hou Zhiqiang
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
The read-only DBI registers can be written over the DBI when set
the "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of the
MISC_CONTROL_1_OFF register.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
drivers/pci/dwc/pcie-designware.h | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index b4d2a89..bbdf35b 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -76,6 +76,9 @@
#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
#define PCIE_ATU_UPPER_TARGET 0x91C
+#define PCIE_MISC_CONTROL_1_OFF 0x8BC
+#define PCIE_DBI_RO_WR_EN (0x1 << 0)
+
/*
* iATU Unroll-specific register definitions
* From 4.80 core version the address translation will be made by unroll
@@ -279,6 +282,28 @@ static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg)
return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4);
}
+static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)
+{
+ u32 reg;
+ u32 val;
+
+ reg = PCIE_MISC_CONTROL_1_OFF;
+ val = dw_pcie_readl_dbi(pci, reg);
+ val |= PCIE_DBI_RO_WR_EN;
+ dw_pcie_writel_dbi(pci, reg, val);
+}
+
+static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
+{
+ u32 reg;
+ u32 val;
+
+ reg = PCIE_MISC_CONTROL_1_OFF;
+ val = dw_pcie_readl_dbi(pci, reg);
+ val &= ~PCIE_DBI_RO_WR_EN;
+ dw_pcie_writel_dbi(pci, reg, val);
+}
+
#ifdef CONFIG_PCIE_DW_HOST
irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
void dw_pcie_msi_init(struct pcie_port *pp);
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 2/3] PCI: designware: enable write permission before updating class code 2017-07-06 6:33 [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers Zhiqiang Hou @ 2017-07-06 6:33 ` Zhiqiang Hou 2017-07-06 6:33 ` [PATCH 3/3] PCI: layerscape: refactor the host_init function Zhiqiang Hou 2017-07-06 9:44 ` [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers Joao Pinto 2 siblings, 0 replies; 13+ messages in thread From: Zhiqiang Hou @ 2017-07-06 6:33 UTC (permalink / raw) To: linux-pci, bhelgaas, jingoohan1, Joao.Pinto; +Cc: Hou Zhiqiang From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> --- drivers/pci/dwc/pcie-designware-host.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c index d29c020..6e10cda 100644 --- a/drivers/pci/dwc/pcie-designware-host.c +++ b/drivers/pci/dwc/pcie-designware-host.c @@ -634,8 +634,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); + /* Enable write permission for the DBI read-only register */ + dw_pcie_dbi_ro_wr_en(pci); /* program correct class for RC */ dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); + /* Better disable write permission right after the update */ + dw_pcie_dbi_ro_wr_dis(pci); dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); val |= PORT_LOGIC_SPEED_CHANGE; -- 2.1.0.27.g96db324 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/3] PCI: layerscape: refactor the host_init function 2017-07-06 6:33 [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers Zhiqiang Hou 2017-07-06 6:33 ` [PATCH 2/3] PCI: designware: enable write permission before updating class code Zhiqiang Hou @ 2017-07-06 6:33 ` Zhiqiang Hou 2017-08-02 21:11 ` Bjorn Helgaas 2017-07-06 9:44 ` [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers Joao Pinto 2 siblings, 1 reply; 13+ messages in thread From: Zhiqiang Hou @ 2017-07-06 6:33 UTC (permalink / raw) To: linux-pci, bhelgaas, jingoohan1, Joao.Pinto; +Cc: Hou Zhiqiang, Minghuan Lian From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Main changes: - Make the ls1021a's host_init reuse layerscape platform's common host_init function. - Will not use the outbound windows configured by bootloader, but introduce DWC common setup function dw_pcie_setup_rc and disable the bootloader configured outbound windows. And remove the duplicate class field fix code. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> --- drivers/pci/dwc/pci-layerscape.c | 85 ++++++++++++++++++++++------------------ 1 file changed, 46 insertions(+), 39 deletions(-) diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c index fd86128..9bed3cd 100644 --- a/drivers/pci/dwc/pci-layerscape.c +++ b/drivers/pci/dwc/pci-layerscape.c @@ -33,7 +33,8 @@ /* PEX Internal Configuration Registers */ #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ -#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */ + +#define PCIE_IATU_NUM 6 struct ls_pcie_drvdata { u32 lut_offset; @@ -69,15 +70,9 @@ static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) { struct dw_pcie *pci = pcie->pci; + dw_pcie_dbi_ro_wr_en(pci); iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE); -} - -/* Fix class value */ -static void ls_pcie_fix_class(struct ls_pcie *pcie) -{ - struct dw_pcie *pci = pcie->pci; - - iowrite16(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE); + dw_pcie_dbi_ro_wr_dis(pci); } /* Drop MSG TLP except for Vendor MSG */ @@ -91,6 +86,14 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) iowrite32(val, pci->dbi_base + PCIE_STRFMR1); } +static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie) +{ + int i; + + for (i = 0; i < PCIE_IATU_NUM; i++) + dw_pcie_disable_atu(pcie->pci, DW_PCIE_REGION_OUTBOUND, i); +} + static int ls1021_pcie_link_up(struct dw_pcie *pci) { u32 state; @@ -108,33 +111,6 @@ static int ls1021_pcie_link_up(struct dw_pcie *pci) return 1; } -static void ls1021_pcie_host_init(struct pcie_port *pp) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct ls_pcie *pcie = to_ls_pcie(pci); - struct device *dev = pci->dev; - u32 index[2]; - - pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, - "fsl,pcie-scfg"); - if (IS_ERR(pcie->scfg)) { - dev_err(dev, "No syscfg phandle specified\n"); - pcie->scfg = NULL; - return; - } - - if (of_property_read_u32_array(dev->of_node, - "fsl,pcie-scfg", index, 2)) { - pcie->scfg = NULL; - return; - } - pcie->index = index[1]; - - dw_pcie_setup_rc(pp); - - ls_pcie_drop_msg_tlp(pcie); -} - static int ls_pcie_link_up(struct dw_pcie *pci) { struct ls_pcie *pcie = to_ls_pcie(pci); @@ -155,11 +131,42 @@ static void ls_pcie_host_init(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct ls_pcie *pcie = to_ls_pcie(pci); - iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN); - ls_pcie_fix_class(pcie); + /* + * Disable the outbound windows configured by bootloader to avoid + * one transaction hitting multiple outbound windows and the function + * dw_pcie_setup_rc will re-configure the outbound windows. + */ + ls_pcie_disable_outbound_atus(pcie); + ls_pcie_clear_multifunction(pcie); ls_pcie_drop_msg_tlp(pcie); - iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN); + + dw_pcie_setup_rc(pp); +} + +static void ls1021_pcie_host_init(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + struct device *dev = pci->dev; + u32 index[2]; + + pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, + "fsl,pcie-scfg"); + if (IS_ERR(pcie->scfg)) { + dev_err(dev, "No syscfg phandle specified\n"); + pcie->scfg = NULL; + return; + } + + if (of_property_read_u32_array(dev->of_node, + "fsl,pcie-scfg", index, 2)) { + pcie->scfg = NULL; + return; + } + pcie->index = index[1]; + + ls_pcie_host_init(pp); } static int ls_pcie_msi_host_init(struct pcie_port *pp, -- 2.1.0.27.g96db324 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 3/3] PCI: layerscape: refactor the host_init function 2017-07-06 6:33 ` [PATCH 3/3] PCI: layerscape: refactor the host_init function Zhiqiang Hou @ 2017-08-02 21:11 ` Bjorn Helgaas 2017-08-03 3:17 ` Z.q. Hou 0 siblings, 1 reply; 13+ messages in thread From: Bjorn Helgaas @ 2017-08-02 21:11 UTC (permalink / raw) To: Zhiqiang Hou; +Cc: linux-pci, bhelgaas, jingoohan1, Joao.Pinto, Minghuan Lian On Thu, Jul 06, 2017 at 02:33:49PM +0800, Zhiqiang Hou wrote: > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > Main changes: > - Make the ls1021a's host_init reuse layerscape platform's common > host_init function. > - Will not use the outbound windows configured by bootloader, but > introduce DWC common setup function dw_pcie_setup_rc and disable > the bootloader configured outbound windows. And remove the duplicate > class field fix code. This seems to have two or even three distinct changes mixed together. Please split them into separate patches. In particular, you mention a class code fix -- that should be its own separate patch. > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> > --- > drivers/pci/dwc/pci-layerscape.c | 85 ++++++++++++++++++++++------------------ > 1 file changed, 46 insertions(+), 39 deletions(-) > > diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c > index fd86128..9bed3cd 100644 > --- a/drivers/pci/dwc/pci-layerscape.c > +++ b/drivers/pci/dwc/pci-layerscape.c > @@ -33,7 +33,8 @@ > > /* PEX Internal Configuration Registers */ > #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ > -#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */ > + > +#define PCIE_IATU_NUM 6 > > struct ls_pcie_drvdata { > u32 lut_offset; > @@ -69,15 +70,9 @@ static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) > { > struct dw_pcie *pci = pcie->pci; > > + dw_pcie_dbi_ro_wr_en(pci); > iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE); > -} > - > -/* Fix class value */ > -static void ls_pcie_fix_class(struct ls_pcie *pcie) > -{ > - struct dw_pcie *pci = pcie->pci; > - > - iowrite16(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE); > + dw_pcie_dbi_ro_wr_dis(pci); > } > > /* Drop MSG TLP except for Vendor MSG */ > @@ -91,6 +86,14 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) > iowrite32(val, pci->dbi_base + PCIE_STRFMR1); > } > > +static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie) > +{ > + int i; > + > + for (i = 0; i < PCIE_IATU_NUM; i++) > + dw_pcie_disable_atu(pcie->pci, DW_PCIE_REGION_OUTBOUND, i); > +} > + > static int ls1021_pcie_link_up(struct dw_pcie *pci) > { > u32 state; > @@ -108,33 +111,6 @@ static int ls1021_pcie_link_up(struct dw_pcie *pci) > return 1; > } > > -static void ls1021_pcie_host_init(struct pcie_port *pp) > -{ > - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > - struct ls_pcie *pcie = to_ls_pcie(pci); > - struct device *dev = pci->dev; > - u32 index[2]; > - > - pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, > - "fsl,pcie-scfg"); > - if (IS_ERR(pcie->scfg)) { > - dev_err(dev, "No syscfg phandle specified\n"); > - pcie->scfg = NULL; > - return; > - } > - > - if (of_property_read_u32_array(dev->of_node, > - "fsl,pcie-scfg", index, 2)) { > - pcie->scfg = NULL; > - return; > - } > - pcie->index = index[1]; > - > - dw_pcie_setup_rc(pp); > - > - ls_pcie_drop_msg_tlp(pcie); > -} > - > static int ls_pcie_link_up(struct dw_pcie *pci) > { > struct ls_pcie *pcie = to_ls_pcie(pci); > @@ -155,11 +131,42 @@ static void ls_pcie_host_init(struct pcie_port *pp) > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > struct ls_pcie *pcie = to_ls_pcie(pci); > > - iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN); > - ls_pcie_fix_class(pcie); > + /* > + * Disable the outbound windows configured by bootloader to avoid > + * one transaction hitting multiple outbound windows and the function > + * dw_pcie_setup_rc will re-configure the outbound windows. > + */ > + ls_pcie_disable_outbound_atus(pcie); > + > ls_pcie_clear_multifunction(pcie); > ls_pcie_drop_msg_tlp(pcie); > - iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN); > + > + dw_pcie_setup_rc(pp); > +} > + > +static void ls1021_pcie_host_init(struct pcie_port *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct ls_pcie *pcie = to_ls_pcie(pci); > + struct device *dev = pci->dev; > + u32 index[2]; > + > + pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, > + "fsl,pcie-scfg"); > + if (IS_ERR(pcie->scfg)) { > + dev_err(dev, "No syscfg phandle specified\n"); > + pcie->scfg = NULL; > + return; > + } > + > + if (of_property_read_u32_array(dev->of_node, > + "fsl,pcie-scfg", index, 2)) { > + pcie->scfg = NULL; > + return; > + } > + pcie->index = index[1]; > + > + ls_pcie_host_init(pp); > } > > static int ls_pcie_msi_host_init(struct pcie_port *pp, > -- > 2.1.0.27.g96db324 > ^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 3/3] PCI: layerscape: refactor the host_init function 2017-08-02 21:11 ` Bjorn Helgaas @ 2017-08-03 3:17 ` Z.q. Hou 0 siblings, 0 replies; 13+ messages in thread From: Z.q. Hou @ 2017-08-03 3:17 UTC (permalink / raw) To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, Joao.Pinto@synopsys.com, M.h. Lian SGkgQmpvcm4sDQoNClRoYW5rcyBhIGxvdCBmb3IgeW91ciBjb21tZW50cyENCg0KPiAtLS0tLU9y aWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9tOiBCam9ybiBIZWxnYWFzIFttYWlsdG86aGVsZ2Fh c0BrZXJuZWwub3JnXQ0KPiBTZW50OiAyMDE3xOo41MIzyNUgNToxMg0KPiBUbzogWi5xLiBIb3Ug PHpoaXFpYW5nLmhvdUBueHAuY29tPg0KPiBDYzogbGludXgtcGNpQHZnZXIua2VybmVsLm9yZzsg YmhlbGdhYXNAZ29vZ2xlLmNvbTsNCj4gamluZ29vaGFuMUBnbWFpbC5jb207IEpvYW8uUGludG9A c3lub3BzeXMuY29tOyBNLmguIExpYW4NCj4gPG1pbmdodWFuLmxpYW5AbnhwLmNvbT4NCj4gU3Vi amVjdDogUmU6IFtQQVRDSCAzLzNdIFBDSTogbGF5ZXJzY2FwZTogcmVmYWN0b3IgdGhlIGhvc3Rf aW5pdCBmdW5jdGlvbg0KPiANCj4gT24gVGh1LCBKdWwgMDYsIDIwMTcgYXQgMDI6MzM6NDlQTSAr MDgwMCwgWmhpcWlhbmcgSG91IHdyb3RlOg0KPiA+IEZyb206IEhvdSBaaGlxaWFuZyA8WmhpcWlh bmcuSG91QG54cC5jb20+DQo+ID4NCj4gPiBNYWluIGNoYW5nZXM6DQo+ID4gLSBNYWtlIHRoZSBs czEwMjFhJ3MgaG9zdF9pbml0IHJldXNlIGxheWVyc2NhcGUgcGxhdGZvcm0ncyBjb21tb24NCj4g PiAgIGhvc3RfaW5pdCBmdW5jdGlvbi4NCj4gPiAtIFdpbGwgbm90IHVzZSB0aGUgb3V0Ym91bmQg d2luZG93cyBjb25maWd1cmVkIGJ5IGJvb3Rsb2FkZXIsIGJ1dA0KPiA+ICAgaW50cm9kdWNlIERX QyBjb21tb24gc2V0dXAgZnVuY3Rpb24gZHdfcGNpZV9zZXR1cF9yYyBhbmQgZGlzYWJsZQ0KPiA+ ICAgdGhlIGJvb3Rsb2FkZXIgY29uZmlndXJlZCBvdXRib3VuZCB3aW5kb3dzLiBBbmQgcmVtb3Zl IHRoZSBkdXBsaWNhdGUNCj4gPiAgIGNsYXNzIGZpZWxkIGZpeCBjb2RlLg0KPiANCj4gVGhpcyBz ZWVtcyB0byBoYXZlIHR3byBvciBldmVuIHRocmVlIGRpc3RpbmN0IGNoYW5nZXMgbWl4ZWQgdG9n ZXRoZXIuDQo+IFBsZWFzZSBzcGxpdCB0aGVtIGludG8gc2VwYXJhdGUgcGF0Y2hlcy4gIEluIHBh cnRpY3VsYXIsIHlvdSBtZW50aW9uIGEgY2xhc3MNCj4gY29kZSBmaXggLS0gdGhhdCBzaG91bGQg YmUgaXRzIG93biBzZXBhcmF0ZSBwYXRjaC4NCg0KWWVzLCB3aWxsIHNwbGl0IHRoaXMgcGF0Y2gu DQoNCj4gPiBTaWduZWQtb2ZmLWJ5OiBIb3UgWmhpcWlhbmcgPFpoaXFpYW5nLkhvdUBueHAuY29t Pg0KPiA+IFNpZ25lZC1vZmYtYnk6IE1pbmdodWFuIExpYW4gPE1pbmdodWFuLkxpYW5AbnhwLmNv bT4NCj4gPiAtLS0NCj4gPiAgZHJpdmVycy9wY2kvZHdjL3BjaS1sYXllcnNjYXBlLmMgfCA4NQ0K PiA+ICsrKysrKysrKysrKysrKysrKysrKystLS0tLS0tLS0tLS0tLS0tLS0NCj4gPiAgMSBmaWxl IGNoYW5nZWQsIDQ2IGluc2VydGlvbnMoKyksIDM5IGRlbGV0aW9ucygtKQ0KPiA+DQo+ID4gZGlm ZiAtLWdpdCBhL2RyaXZlcnMvcGNpL2R3Yy9wY2ktbGF5ZXJzY2FwZS5jDQo+ID4gYi9kcml2ZXJz L3BjaS9kd2MvcGNpLWxheWVyc2NhcGUuYw0KPiA+IGluZGV4IGZkODYxMjguLjliZWQzY2QgMTAw NjQ0DQo+ID4gLS0tIGEvZHJpdmVycy9wY2kvZHdjL3BjaS1sYXllcnNjYXBlLmMNCj4gPiArKysg Yi9kcml2ZXJzL3BjaS9kd2MvcGNpLWxheWVyc2NhcGUuYw0KPiA+IEBAIC0zMyw3ICszMyw4IEBA DQo+ID4NCj4gPiAgLyogUEVYIEludGVybmFsIENvbmZpZ3VyYXRpb24gUmVnaXN0ZXJzICovDQo+ ID4gICNkZWZpbmUgUENJRV9TVFJGTVIxCQkweDcxYyAvKiBTeW1ib2wgVGltZXIgJiBGaWx0ZXIg TWFzaw0KPiBSZWdpc3RlcjEgKi8NCj4gPiAtI2RlZmluZSBQQ0lFX0RCSV9ST19XUl9FTgkweDhi YyAvKiBEQkkgUmVhZC1Pbmx5IFdyaXRlIEVuYWJsZQ0KPiBSZWdpc3RlciAqLw0KPiA+ICsNCj4g PiArI2RlZmluZSBQQ0lFX0lBVFVfTlVNCQk2DQo+ID4NCj4gPiAgc3RydWN0IGxzX3BjaWVfZHJ2 ZGF0YSB7DQo+ID4gIAl1MzIgbHV0X29mZnNldDsNCj4gPiBAQCAtNjksMTUgKzcwLDkgQEAgc3Rh dGljIHZvaWQgbHNfcGNpZV9jbGVhcl9tdWx0aWZ1bmN0aW9uKHN0cnVjdA0KPiA+IGxzX3BjaWUg KnBjaWUpICB7DQo+ID4gIAlzdHJ1Y3QgZHdfcGNpZSAqcGNpID0gcGNpZS0+cGNpOw0KPiA+DQo+ ID4gKwlkd19wY2llX2RiaV9yb193cl9lbihwY2kpOw0KPiA+ICAJaW93cml0ZTgoUENJX0hFQURF Ul9UWVBFX0JSSURHRSwgcGNpLT5kYmlfYmFzZSArDQo+IFBDSV9IRUFERVJfVFlQRSk7DQo+ID4g LX0NCj4gPiAtDQo+ID4gLS8qIEZpeCBjbGFzcyB2YWx1ZSAqLw0KPiA+IC1zdGF0aWMgdm9pZCBs c19wY2llX2ZpeF9jbGFzcyhzdHJ1Y3QgbHNfcGNpZSAqcGNpZSkgLXsNCj4gPiAtCXN0cnVjdCBk d19wY2llICpwY2kgPSBwY2llLT5wY2k7DQo+ID4gLQ0KPiA+IC0JaW93cml0ZTE2KFBDSV9DTEFT U19CUklER0VfUENJLCBwY2ktPmRiaV9iYXNlICsgUENJX0NMQVNTX0RFVklDRSk7DQo+ID4gKwlk d19wY2llX2RiaV9yb193cl9kaXMocGNpKTsNCj4gPiAgfQ0KPiA+DQo+ID4gIC8qIERyb3AgTVNH IFRMUCBleGNlcHQgZm9yIFZlbmRvciBNU0cgKi8gQEAgLTkxLDYgKzg2LDE0IEBAIHN0YXRpYw0K PiA+IHZvaWQgbHNfcGNpZV9kcm9wX21zZ190bHAoc3RydWN0IGxzX3BjaWUgKnBjaWUpDQo+ID4g IAlpb3dyaXRlMzIodmFsLCBwY2ktPmRiaV9iYXNlICsgUENJRV9TVFJGTVIxKTsgIH0NCj4gPg0K PiA+ICtzdGF0aWMgdm9pZCBsc19wY2llX2Rpc2FibGVfb3V0Ym91bmRfYXR1cyhzdHJ1Y3QgbHNf cGNpZSAqcGNpZSkgew0KPiA+ICsJaW50IGk7DQo+ID4gKw0KPiA+ICsJZm9yIChpID0gMDsgaSA8 IFBDSUVfSUFUVV9OVU07IGkrKykNCj4gPiArCQlkd19wY2llX2Rpc2FibGVfYXR1KHBjaWUtPnBj aSwgRFdfUENJRV9SRUdJT05fT1VUQk9VTkQsIGkpOyB9DQo+ID4gKw0KPiA+ICBzdGF0aWMgaW50 IGxzMTAyMV9wY2llX2xpbmtfdXAoc3RydWN0IGR3X3BjaWUgKnBjaSkgIHsNCj4gPiAgCXUzMiBz dGF0ZTsNCj4gPiBAQCAtMTA4LDMzICsxMTEsNiBAQCBzdGF0aWMgaW50IGxzMTAyMV9wY2llX2xp bmtfdXAoc3RydWN0IGR3X3BjaWUgKnBjaSkNCj4gPiAgCXJldHVybiAxOw0KPiA+ICB9DQo+ID4N Cj4gPiAtc3RhdGljIHZvaWQgbHMxMDIxX3BjaWVfaG9zdF9pbml0KHN0cnVjdCBwY2llX3BvcnQg KnBwKSAtew0KPiA+IC0Jc3RydWN0IGR3X3BjaWUgKnBjaSA9IHRvX2R3X3BjaWVfZnJvbV9wcChw cCk7DQo+ID4gLQlzdHJ1Y3QgbHNfcGNpZSAqcGNpZSA9IHRvX2xzX3BjaWUocGNpKTsNCj4gPiAt CXN0cnVjdCBkZXZpY2UgKmRldiA9IHBjaS0+ZGV2Ow0KPiA+IC0JdTMyIGluZGV4WzJdOw0KPiA+ IC0NCj4gPiAtCXBjaWUtPnNjZmcgPSBzeXNjb25fcmVnbWFwX2xvb2t1cF9ieV9waGFuZGxlKGRl di0+b2Zfbm9kZSwNCj4gPiAtCQkJCQkJICAgICAiZnNsLHBjaWUtc2NmZyIpOw0KPiA+IC0JaWYg KElTX0VSUihwY2llLT5zY2ZnKSkgew0KPiA+IC0JCWRldl9lcnIoZGV2LCAiTm8gc3lzY2ZnIHBo YW5kbGUgc3BlY2lmaWVkXG4iKTsNCj4gPiAtCQlwY2llLT5zY2ZnID0gTlVMTDsNCj4gPiAtCQly ZXR1cm47DQo+ID4gLQl9DQo+ID4gLQ0KPiA+IC0JaWYgKG9mX3Byb3BlcnR5X3JlYWRfdTMyX2Fy cmF5KGRldi0+b2Zfbm9kZSwNCj4gPiAtCQkJCSAgICAgICAiZnNsLHBjaWUtc2NmZyIsIGluZGV4 LCAyKSkgew0KPiA+IC0JCXBjaWUtPnNjZmcgPSBOVUxMOw0KPiA+IC0JCXJldHVybjsNCj4gPiAt CX0NCj4gPiAtCXBjaWUtPmluZGV4ID0gaW5kZXhbMV07DQo+ID4gLQ0KPiA+IC0JZHdfcGNpZV9z ZXR1cF9yYyhwcCk7DQo+ID4gLQ0KPiA+IC0JbHNfcGNpZV9kcm9wX21zZ190bHAocGNpZSk7DQo+ ID4gLX0NCj4gPiAtDQo+ID4gIHN0YXRpYyBpbnQgbHNfcGNpZV9saW5rX3VwKHN0cnVjdCBkd19w Y2llICpwY2kpICB7DQo+ID4gIAlzdHJ1Y3QgbHNfcGNpZSAqcGNpZSA9IHRvX2xzX3BjaWUocGNp KTsgQEAgLTE1NSwxMSArMTMxLDQyIEBAIHN0YXRpYw0KPiA+IHZvaWQgbHNfcGNpZV9ob3N0X2lu aXQoc3RydWN0IHBjaWVfcG9ydCAqcHApDQo+ID4gIAlzdHJ1Y3QgZHdfcGNpZSAqcGNpID0gdG9f ZHdfcGNpZV9mcm9tX3BwKHBwKTsNCj4gPiAgCXN0cnVjdCBsc19wY2llICpwY2llID0gdG9fbHNf cGNpZShwY2kpOw0KPiA+DQo+ID4gLQlpb3dyaXRlMzIoMSwgcGNpLT5kYmlfYmFzZSArIFBDSUVf REJJX1JPX1dSX0VOKTsNCj4gPiAtCWxzX3BjaWVfZml4X2NsYXNzKHBjaWUpOw0KPiA+ICsJLyoN Cj4gPiArCSAqIERpc2FibGUgdGhlIG91dGJvdW5kIHdpbmRvd3MgY29uZmlndXJlZCBieSBib290 bG9hZGVyIHRvIGF2b2lkDQo+ID4gKwkgKiBvbmUgdHJhbnNhY3Rpb24gaGl0dGluZyBtdWx0aXBs ZSBvdXRib3VuZCB3aW5kb3dzIGFuZCB0aGUgZnVuY3Rpb24NCj4gPiArCSAqIGR3X3BjaWVfc2V0 dXBfcmMgd2lsbCByZS1jb25maWd1cmUgdGhlIG91dGJvdW5kIHdpbmRvd3MuDQo+ID4gKwkgKi8N Cj4gPiArCWxzX3BjaWVfZGlzYWJsZV9vdXRib3VuZF9hdHVzKHBjaWUpOw0KPiA+ICsNCj4gPiAg CWxzX3BjaWVfY2xlYXJfbXVsdGlmdW5jdGlvbihwY2llKTsNCj4gPiAgCWxzX3BjaWVfZHJvcF9t c2dfdGxwKHBjaWUpOw0KPiA+IC0JaW93cml0ZTMyKDAsIHBjaS0+ZGJpX2Jhc2UgKyBQQ0lFX0RC SV9ST19XUl9FTik7DQo+ID4gKw0KPiA+ICsJZHdfcGNpZV9zZXR1cF9yYyhwcCk7DQo+ID4gK30N Cj4gPiArDQo+ID4gK3N0YXRpYyB2b2lkIGxzMTAyMV9wY2llX2hvc3RfaW5pdChzdHJ1Y3QgcGNp ZV9wb3J0ICpwcCkgew0KPiA+ICsJc3RydWN0IGR3X3BjaWUgKnBjaSA9IHRvX2R3X3BjaWVfZnJv bV9wcChwcCk7DQo+ID4gKwlzdHJ1Y3QgbHNfcGNpZSAqcGNpZSA9IHRvX2xzX3BjaWUocGNpKTsN Cj4gPiArCXN0cnVjdCBkZXZpY2UgKmRldiA9IHBjaS0+ZGV2Ow0KPiA+ICsJdTMyIGluZGV4WzJd Ow0KPiA+ICsNCj4gPiArCXBjaWUtPnNjZmcgPSBzeXNjb25fcmVnbWFwX2xvb2t1cF9ieV9waGFu ZGxlKGRldi0+b2Zfbm9kZSwNCj4gPiArCQkJCQkJICAgICAiZnNsLHBjaWUtc2NmZyIpOw0KPiA+ ICsJaWYgKElTX0VSUihwY2llLT5zY2ZnKSkgew0KPiA+ICsJCWRldl9lcnIoZGV2LCAiTm8gc3lz Y2ZnIHBoYW5kbGUgc3BlY2lmaWVkXG4iKTsNCj4gPiArCQlwY2llLT5zY2ZnID0gTlVMTDsNCj4g PiArCQlyZXR1cm47DQo+ID4gKwl9DQo+ID4gKw0KPiA+ICsJaWYgKG9mX3Byb3BlcnR5X3JlYWRf dTMyX2FycmF5KGRldi0+b2Zfbm9kZSwNCj4gPiArCQkJCSAgICAgICAiZnNsLHBjaWUtc2NmZyIs IGluZGV4LCAyKSkgew0KPiA+ICsJCXBjaWUtPnNjZmcgPSBOVUxMOw0KPiA+ICsJCXJldHVybjsN Cj4gPiArCX0NCj4gPiArCXBjaWUtPmluZGV4ID0gaW5kZXhbMV07DQo+ID4gKw0KPiA+ICsJbHNf cGNpZV9ob3N0X2luaXQocHApOw0KPiA+ICB9DQo+ID4NCj4gPiAgc3RhdGljIGludCBsc19wY2ll X21zaV9ob3N0X2luaXQoc3RydWN0IHBjaWVfcG9ydCAqcHAsDQo+ID4gLS0NCj4gPiAyLjEuMC4y Ny5nOTZkYjMyNA0KPiA+DQoNClRoYW5rcywNClpoaXFpYW5nDQo= ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers 2017-07-06 6:33 [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers Zhiqiang Hou 2017-07-06 6:33 ` [PATCH 2/3] PCI: designware: enable write permission before updating class code Zhiqiang Hou 2017-07-06 6:33 ` [PATCH 3/3] PCI: layerscape: refactor the host_init function Zhiqiang Hou @ 2017-07-06 9:44 ` Joao Pinto 2017-07-07 3:48 ` Z.q. Hou 2017-08-02 21:25 ` Bjorn Helgaas 2 siblings, 2 replies; 13+ messages in thread From: Joao Pinto @ 2017-07-06 9:44 UTC (permalink / raw) To: Zhiqiang Hou, linux-pci, Joao.Pinto; +Cc: bhelgaas, jingoohan1 Hi Zhiqiang, Às 7:33 AM de 7/6/2017, Zhiqiang Hou escreveu: > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > The read-only DBI registers can be written over the DBI when set > the "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of the > MISC_CONTROL_1_OFF register. I would suggest you to add a cover-letter next time to explain the global picture of the patch-set. I understand your need for this patch, but I don't agree on the approach. Sometimes the people in charge of the hardware design / configuration, forget to specify the device class and that can be problematic for some drivers, and so the typical workaround is to set it in the driver using a quirk for example. You can see some examples here: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/quirks.c Thanks, Joao > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > --- > drivers/pci/dwc/pcie-designware.h | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h > index b4d2a89..bbdf35b 100644 > --- a/drivers/pci/dwc/pcie-designware.h > +++ b/drivers/pci/dwc/pcie-designware.h > @@ -76,6 +76,9 @@ > #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) > #define PCIE_ATU_UPPER_TARGET 0x91C > > +#define PCIE_MISC_CONTROL_1_OFF 0x8BC > +#define PCIE_DBI_RO_WR_EN (0x1 << 0) > + > /* > * iATU Unroll-specific register definitions > * From 4.80 core version the address translation will be made by unroll > @@ -279,6 +282,28 @@ static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg) > return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4); > } > > +static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci) > +{ > + u32 reg; > + u32 val; > + > + reg = PCIE_MISC_CONTROL_1_OFF; > + val = dw_pcie_readl_dbi(pci, reg); > + val |= PCIE_DBI_RO_WR_EN; > + dw_pcie_writel_dbi(pci, reg, val); > +} > + > +static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci) > +{ > + u32 reg; > + u32 val; > + > + reg = PCIE_MISC_CONTROL_1_OFF; > + val = dw_pcie_readl_dbi(pci, reg); > + val &= ~PCIE_DBI_RO_WR_EN; > + dw_pcie_writel_dbi(pci, reg, val); > +} > + > #ifdef CONFIG_PCIE_DW_HOST > irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); > void dw_pcie_msi_init(struct pcie_port *pp); > ^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers 2017-07-06 9:44 ` [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers Joao Pinto @ 2017-07-07 3:48 ` Z.q. Hou 2017-07-07 8:53 ` Joao Pinto 2017-08-02 21:25 ` Bjorn Helgaas 1 sibling, 1 reply; 13+ messages in thread From: Z.q. Hou @ 2017-07-07 3:48 UTC (permalink / raw) To: Joao Pinto, linux-pci@vger.kernel.org Cc: bhelgaas@google.com, jingoohan1@gmail.com SGkgSm9hbywNCg0KVGhhbmtzIGEgbG90IGZvciB5b3VyIGNvbW1lbnRzIQ0KDQo+IC0tLS0tT3Jp Z2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IEpvYW8gUGludG8gW21haWx0bzpKb2FvLlBpbnRv QHN5bm9wc3lzLmNvbV0NCj4gU2VudDogMjAxN+W5tDfmnIg25pelIDE3OjQ0DQo+IFRvOiBaLnEu IEhvdSA8emhpcWlhbmcuaG91QG54cC5jb20+OyBsaW51eC1wY2lAdmdlci5rZXJuZWwub3JnOw0K PiBKb2FvLlBpbnRvQHN5bm9wc3lzLmNvbQ0KPiBDYzogYmhlbGdhYXNAZ29vZ2xlLmNvbTsgamlu Z29vaGFuMUBnbWFpbC5jb20NCj4gU3ViamVjdDogUmU6IFtQQVRDSCAxLzNdIFBDSTogZGVzaWdu d2FyZTogYWRkIGFjY2Vzc29ycyBmb3Igd3JpdGUgcGVybWlzc2lvbg0KPiBvZiBEQkkgcmVhZC1v bmx5IHJlZ2lzdGVycw0KPiANCj4gDQo+IEhpIFpoaXFpYW5nLA0KPiANCj4gw4BzIDc6MzMgQU0g ZGUgNy82LzIwMTcsIFpoaXFpYW5nIEhvdSBlc2NyZXZldToNCj4gPiBGcm9tOiBIb3UgWmhpcWlh bmcgPFpoaXFpYW5nLkhvdUBueHAuY29tPg0KPiA+DQo+ID4gVGhlIHJlYWQtb25seSBEQkkgcmVn aXN0ZXJzIGNhbiBiZSB3cml0dGVuIG92ZXIgdGhlIERCSSB3aGVuIHNldCB0aGUNCj4gPiAiV3Jp dGUgdG8gUk8gUmVnaXN0ZXJzIFVzaW5nIERCSSIgKERCSV9ST19XUl9FTikgZmllbGQgb2YgdGhl DQo+ID4gTUlTQ19DT05UUk9MXzFfT0ZGIHJlZ2lzdGVyLg0KPiANCj4gSSB3b3VsZCBzdWdnZXN0 IHlvdSB0byBhZGQgYSBjb3Zlci1sZXR0ZXIgbmV4dCB0aW1lIHRvIGV4cGxhaW4gdGhlIGdsb2Jh bA0KPiBwaWN0dXJlIG9mIHRoZSBwYXRjaC1zZXQuDQoNClRoYW5rcywgSSB3aWxsLg0KDQo+IA0K PiBJIHVuZGVyc3RhbmQgeW91ciBuZWVkIGZvciB0aGlzIHBhdGNoLCBidXQgSSBkb24ndCBhZ3Jl ZSBvbiB0aGUgYXBwcm9hY2guDQoNCkluIHRoZSBEV0MgY29tbW9uIGNvZGUsIHRoZXJlIGlzIGEg ZnVuY3Rpb24gd3JpdGUgYSBEQkkgcmVhZC1vbmx5IHJlZ2lzdGVyICdEZXZpY2UgY2xhc3MgY29k ZScsIGFuZCB0aGUgZmlyc3QgMiBwYXRjaGVzIGlzIHRvIGZpeCBpdC4NClRoZSAzcmQgcGF0Y2gg aXMgdG8gcmVmYWN0b3IgdGhlIExheWVyc2NhcGUgUENJZSBkcml2ZXIncyBob3N0X2luaXQgZnVu Y3Rpb24gYW5kIHJldXNlIHRoZSBuZXcgYWRkZWQgYWNjZXNzb3JzLg0KDQo+IFNvbWV0aW1lcyB0 aGUgcGVvcGxlIGluIGNoYXJnZSBvZiB0aGUgaGFyZHdhcmUgZGVzaWduIC8gY29uZmlndXJhdGlv biwgZm9yZ2V0DQo+IHRvIHNwZWNpZnkgdGhlIGRldmljZSBjbGFzcyBhbmQgdGhhdCBjYW4gYmUg cHJvYmxlbWF0aWMgZm9yIHNvbWUgZHJpdmVycywgYW5kDQo+IHNvIHRoZSB0eXBpY2FsIHdvcmth cm91bmQgaXMgdG8gc2V0IGl0IGluIHRoZSBkcml2ZXIgdXNpbmcgYSBxdWlyayBmb3IgZXhhbXBs ZS4NCj4gDQo+IFlvdSBjYW4gc2VlIHNvbWUgZXhhbXBsZXMgaGVyZToNCj4gaHR0cHM6Ly9naXQu a2VybmVsLm9yZy9wdWIvc2NtL2xpbnV4L2tlcm5lbC9naXQvdG9ydmFsZHMvbGludXguZ2l0L3Ry ZWUvZHJpdmVycy8NCj4gcGNpL3F1aXJrcy5jDQoNCkkgZG9uJ3Qga25vdyB0aGUgUENJIHF1aXJr cywgZG8geW91IG1lYW4gcmVtb3ZlIHRoZSBwY2kgRGV2aWNlIENsYXNzIGZpeCBjb2RlIGZyb20g dGhlIERXQyBjb21tb24gY29kZSBhbmQgYWRkIGl0IHRvIHF1aXJrcz8gIA0KDQpUaGFua3MsDQpa aGlxaWFuZyANCg== ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers 2017-07-07 3:48 ` Z.q. Hou @ 2017-07-07 8:53 ` Joao Pinto 2017-07-11 4:11 ` Z.q. Hou 0 siblings, 1 reply; 13+ messages in thread From: Joao Pinto @ 2017-07-07 8:53 UTC (permalink / raw) To: Z.q. Hou, Joao Pinto, linux-pci@vger.kernel.org, bhelgaas@google.com Cc: jingoohan1@gmail.com Hi Zhiqiang, Às 4:48 AM de 7/7/2017, Z.q. Hou escreveu: > Hi Joao, > > > > Thanks a lot for your comments! > > > >> -----Original Message----- > >> From: Joao Pinto [mailto:Joao.Pinto@synopsys.com] > >> Sent: 2017年7月6日 17:44 > >> To: Z.q. Hou <zhiqiang.hou@nxp.com>; linux-pci@vger.kernel.org; > >> Joao.Pinto@synopsys.com > >> Cc: bhelgaas@google.com; jingoohan1@gmail.com > >> Subject: Re: [PATCH 1/3] PCI: designware: add accessors for write permission > >> of DBI read-only registers > >> > >> > >> Hi Zhiqiang, > >> > >> Às 7:33 AM de 7/6/2017, Zhiqiang Hou escreveu: > >>> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > >>> > >>> The read-only DBI registers can be written over the DBI when set the > >>> "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of the > >>> MISC_CONTROL_1_OFF register. > >> > >> I would suggest you to add a cover-letter next time to explain the global > >> picture of the patch-set. > > > > Thanks, I will. > > > >> > >> I understand your need for this patch, but I don't agree on the approach. > > > > In the DWC common code, there is a function write a DBI read-only register 'Device class code', and the first 2 patches is to fix it. > > The 3rd patch is to refactor the Layerscape PCIe driver's host_init function and reuse the new added accessors. > > > >> Sometimes the people in charge of the hardware design / configuration, forget > >> to specify the device class and that can be problematic for some drivers, and > >> so the typical workaround is to set it in the driver using a quirk for example. > >> > >> You can see some examples here: > >> https://urldefense.proofpoint.com/v2/url?u=https-3A__git.kernel.org_pub_scm_linux_kernel_git_torvalds_linux.git_tree_drivers_&d=DwIGaQ&c=DPL6_X_6JkXFx7AXWqB0tg&r=s2fO0hii0OGNOv9qQy_HRXy-xAJUD1NNoEcc3io_kx0&m=0DrBCvOc_J7LaMXBei1qCXxxfbLxWaVErKZ6Rkm6bUc&s=sOEmExQFqrCEmpAx9LjSeKRvkW1D-W82ckX5WGCgFWw&e= > >> pci/quirks.c > > > > I don't know the PCI quirks, do you mean remove the pci Device Class fix code from the DWC common code and add it to quirks? > In my opinion adding fixes to a common code is not a good approach. I would suggest the fix to go into the quirks file. @Bjorn: The quirks file is the best place for this type of fixes right? Thanks, Joao > > > Thanks, > > Zhiqiang > ^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers 2017-07-07 8:53 ` Joao Pinto @ 2017-07-11 4:11 ` Z.q. Hou 2017-07-17 19:41 ` Jingoo Han 0 siblings, 1 reply; 13+ messages in thread From: Z.q. Hou @ 2017-07-11 4:11 UTC (permalink / raw) To: Joao Pinto, linux-pci@vger.kernel.org, bhelgaas@google.com Cc: jingoohan1@gmail.com SGkgQmpvcm4sDQoNCkR1ZSB0byBhbGwgRnJlZXNjYWxlIExheWVyc2NwZSBQQ0llIGNvbnRyb2xs ZXJzIGhhdmUgdG8gZml4IHRoZSBDbGFzcyBjb2RlLCBhbmQgdGhpcyBmaXh1cCBleGlzdGVkIGlu IGJvdGggTGF5ZXJzY2FwZSBwY2llIGRyaXZlciBhbmQgRFdDIGNvbW1vbiBjb2RlLCBzbyBJIHdh bnQgdG8gcmV1c2UgdGhlIGZpeHVwIGluIERXQyBjb21tb24gY29kZS4NCkNhbiB5b3UgZ2l2ZSBt ZSBhbnkgc3VnZ2VzdGlvbj8NCg0KPiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9t OiBKb2FvIFBpbnRvIFttYWlsdG86Sm9hby5QaW50b0BzeW5vcHN5cy5jb21dDQo+IFNlbnQ6IDIw MTflubQ35pyIN+aXpSAxNjo1Mw0KPiBUbzogWi5xLiBIb3UgPHpoaXFpYW5nLmhvdUBueHAuY29t PjsgSm9hbyBQaW50bw0KPiA8Sm9hby5QaW50b0BzeW5vcHN5cy5jb20+OyBsaW51eC1wY2lAdmdl ci5rZXJuZWwub3JnOw0KPiBiaGVsZ2Fhc0Bnb29nbGUuY29tDQo+IENjOiBqaW5nb29oYW4xQGdt YWlsLmNvbQ0KPiBTdWJqZWN0OiBSZTogW1BBVENIIDEvM10gUENJOiBkZXNpZ253YXJlOiBhZGQg YWNjZXNzb3JzIGZvciB3cml0ZSBwZXJtaXNzaW9uDQo+IG9mIERCSSByZWFkLW9ubHkgcmVnaXN0 ZXJzDQo+IA0KPiANCj4gSGkgWmhpcWlhbmcsDQo+IA0KPiDDgHMgNDo0OCBBTSBkZSA3LzcvMjAx NywgWi5xLiBIb3UgZXNjcmV2ZXU6DQo+ID4gSGkgSm9hbywNCj4gPg0KPiA+DQo+ID4NCj4gPiBU aGFua3MgYSBsb3QgZm9yIHlvdXIgY29tbWVudHMhDQo+ID4NCj4gPg0KPiA+DQo+ID4+IC0tLS0t T3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+ID4NCj4gPj4gRnJvbTogSm9hbyBQaW50byBbbWFpbHRv OkpvYW8uUGludG9Ac3lub3BzeXMuY29tXQ0KPiA+DQo+ID4+IFNlbnQ6IDIwMTflubQ35pyINuaX pSAxNzo0NA0KPiA+DQo+ID4+IFRvOiBaLnEuIEhvdSA8emhpcWlhbmcuaG91QG54cC5jb20+OyBs aW51eC1wY2lAdmdlci5rZXJuZWwub3JnOw0KPiA+DQo+ID4+IEpvYW8uUGludG9Ac3lub3BzeXMu Y29tDQo+ID4NCj4gPj4gQ2M6IGJoZWxnYWFzQGdvb2dsZS5jb207IGppbmdvb2hhbjFAZ21haWwu Y29tDQo+ID4NCj4gPj4gU3ViamVjdDogUmU6IFtQQVRDSCAxLzNdIFBDSTogZGVzaWdud2FyZTog YWRkIGFjY2Vzc29ycyBmb3Igd3JpdGUNCj4gPj4gcGVybWlzc2lvbg0KPiA+DQo+ID4+IG9mIERC SSByZWFkLW9ubHkgcmVnaXN0ZXJzDQo+ID4NCj4gPj4NCj4gPg0KPiA+Pg0KPiA+DQo+ID4+IEhp IFpoaXFpYW5nLA0KPiA+DQo+ID4+DQo+ID4NCj4gPj4gw4BzIDc6MzMgQU0gZGUgNy82LzIwMTcs IFpoaXFpYW5nIEhvdSBlc2NyZXZldToNCj4gPg0KPiA+Pj4gRnJvbTogSG91IFpoaXFpYW5nIDxa aGlxaWFuZy5Ib3VAbnhwLmNvbT4NCj4gPg0KPiA+Pj4NCj4gPg0KPiA+Pj4gVGhlIHJlYWQtb25s eSBEQkkgcmVnaXN0ZXJzIGNhbiBiZSB3cml0dGVuIG92ZXIgdGhlIERCSSB3aGVuIHNldCB0aGUN Cj4gPg0KPiA+Pj4gIldyaXRlIHRvIFJPIFJlZ2lzdGVycyBVc2luZyBEQkkiIChEQklfUk9fV1Jf RU4pIGZpZWxkIG9mIHRoZQ0KPiA+DQo+ID4+PiBNSVNDX0NPTlRST0xfMV9PRkYgcmVnaXN0ZXIu DQo+ID4NCj4gPj4NCj4gPg0KPiA+PiBJIHdvdWxkIHN1Z2dlc3QgeW91IHRvIGFkZCBhIGNvdmVy LWxldHRlciBuZXh0IHRpbWUgdG8gZXhwbGFpbiB0aGUNCj4gPj4gZ2xvYmFsDQo+ID4NCj4gPj4g cGljdHVyZSBvZiB0aGUgcGF0Y2gtc2V0Lg0KPiA+DQo+ID4NCj4gPg0KPiA+IFRoYW5rcywgSSB3 aWxsLg0KPiA+DQo+ID4NCj4gPg0KPiA+Pg0KPiA+DQo+ID4+IEkgdW5kZXJzdGFuZCB5b3VyIG5l ZWQgZm9yIHRoaXMgcGF0Y2gsIGJ1dCBJIGRvbid0IGFncmVlIG9uIHRoZSBhcHByb2FjaC4NCj4g Pg0KPiA+DQo+ID4NCj4gPiBJbiB0aGUgRFdDIGNvbW1vbiBjb2RlLCB0aGVyZSBpcyBhIGZ1bmN0 aW9uIHdyaXRlIGEgREJJIHJlYWQtb25seSByZWdpc3Rlcg0KPiAnRGV2aWNlIGNsYXNzIGNvZGUn LCBhbmQgdGhlIGZpcnN0IDIgcGF0Y2hlcyBpcyB0byBmaXggaXQuDQo+ID4NCj4gPiBUaGUgM3Jk IHBhdGNoIGlzIHRvIHJlZmFjdG9yIHRoZSBMYXllcnNjYXBlIFBDSWUgZHJpdmVyJ3MgaG9zdF9p bml0IGZ1bmN0aW9uDQo+IGFuZCByZXVzZSB0aGUgbmV3IGFkZGVkIGFjY2Vzc29ycy4NCj4gPg0K PiA+DQo+ID4NCj4gPj4gU29tZXRpbWVzIHRoZSBwZW9wbGUgaW4gY2hhcmdlIG9mIHRoZSBoYXJk d2FyZSBkZXNpZ24gLw0KPiA+PiBjb25maWd1cmF0aW9uLCBmb3JnZXQNCj4gPg0KPiA+PiB0byBz cGVjaWZ5IHRoZSBkZXZpY2UgY2xhc3MgYW5kIHRoYXQgY2FuIGJlIHByb2JsZW1hdGljIGZvciBz b21lDQo+ID4+IGRyaXZlcnMsIGFuZA0KPiA+DQo+ID4+IHNvIHRoZSB0eXBpY2FsIHdvcmthcm91 bmQgaXMgdG8gc2V0IGl0IGluIHRoZSBkcml2ZXIgdXNpbmcgYSBxdWlyayBmb3IgZXhhbXBsZS4N Cj4gPg0KPiA+Pg0KPiA+DQo+ID4+IFlvdSBjYW4gc2VlIHNvbWUgZXhhbXBsZXMgaGVyZToNCj4g Pg0KPiA+PiBodHRwczovL3VybGRlZmVuc2UucHJvb2Zwb2ludC5jb20vdjIvdXJsP3U9aHR0cHMt M0FfX2dpdC5rZXJuZWwub3JnX3ANCj4gPj4gdWJfc2NtX2xpbnV4X2tlcm5lbF9naXRfdG9ydmFs ZHNfbGludXguZ2l0X3RyZWVfZHJpdmVyc18mZD1Ed0lHYVEmYz1EDQo+ID4+DQo+IFBMNl9YXzZK a1hGeDdBWFdxQjB0ZyZyPXMyZk8waGlpME9HTk92OXFReV9IUlh5LXhBSlVEMU5Ob0VjYzNpbw0K PiBfa3gwJm0NCj4gPj4NCj4gPTBEckJDdk9jX0o3TGFNWEJlaTFxQ1h4eGZiTHhXYVZFcktaNlJr bTZiVWMmcz1zT0VtRXhRRnFyQ0VtcEENCj4geDlMalNlSw0KPiA+PiBSdmtXMUQtVzgyY2tYNVdH Q2dGV3cmZT0NCj4gPg0KPiA+PiBwY2kvcXVpcmtzLmMNCj4gPg0KPiA+DQo+ID4NCj4gPiBJIGRv bid0IGtub3cgdGhlIFBDSSBxdWlya3MsIGRvIHlvdSBtZWFuIHJlbW92ZSB0aGUgcGNpIERldmlj ZSBDbGFzcyBmaXgNCj4gY29kZSBmcm9tIHRoZSBEV0MgY29tbW9uIGNvZGUgYW5kIGFkZCBpdCB0 byBxdWlya3M/DQo+ID4NCj4gDQo+IEluIG15IG9waW5pb24gYWRkaW5nIGZpeGVzIHRvIGEgY29t bW9uIGNvZGUgaXMgbm90IGEgZ29vZCBhcHByb2FjaC4gSSB3b3VsZA0KPiBzdWdnZXN0IHRoZSBm aXggdG8gZ28gaW50byB0aGUgcXVpcmtzIGZpbGUuDQo+IA0KPiBAQmpvcm46IFRoZSBxdWlya3Mg ZmlsZSBpcyB0aGUgYmVzdCBwbGFjZSBmb3IgdGhpcyB0eXBlIG9mIGZpeGVzIHJpZ2h0Pw0KDQpU aGFua3MsDQpaaGlxaWFuZw0KDQoNCg== ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers 2017-07-11 4:11 ` Z.q. Hou @ 2017-07-17 19:41 ` Jingoo Han 2017-07-18 3:00 ` Z.q. Hou 0 siblings, 1 reply; 13+ messages in thread From: Jingoo Han @ 2017-07-17 19:41 UTC (permalink / raw) To: 'Z.q. Hou', 'Joao Pinto', linux-pci, bhelgaas On Tuesday, July 11, 2017 12:11 AM, Z.q. Hou wrote: >=20 > Hi Bjorn, >=20 > Due to all Freescale Layerscpe PCIe controllers have to fix the Class = code, > and this fixup existed in both Layerscape pcie driver and DWC common = code, > so I want to reuse the fixup in DWC common code. > Can you give me any suggestion? Please don't add your comment on top of the email. >=20 > > -----Original Message----- > > From: Joao Pinto [mailto:Joao.Pinto@synopsys.com] > > Sent: 2017=E5=B9=B47=E6=9C=887=E6=97=A5 16:53 > > To: Z.q. Hou <zhiqiang.hou@nxp.com>; Joao Pinto > > <Joao.Pinto@synopsys.com>; linux-pci@vger.kernel.org; > > bhelgaas@google.com > > Cc: jingoohan1@gmail.com > > Subject: Re: [PATCH 1/3] PCI: designware: add accessors for write > permission > > of DBI read-only registers > > > > > > Hi Zhiqiang, > > > > =C3=80s 4:48 AM de 7/7/2017, Z.q. Hou escreveu: > > > Hi Joao, > > > > > > > > > > > > Thanks a lot for your comments! > > > > > > > > > > > >> -----Original Message----- > > > > > >> From: Joao Pinto [mailto:Joao.Pinto@synopsys.com] > > > > > >> Sent: 2017=E5=B9=B47=E6=9C=886=E6=97=A5 17:44 > > > > > >> To: Z.q. Hou <zhiqiang.hou@nxp.com>; linux-pci@vger.kernel.org; > > > > > >> Joao.Pinto@synopsys.com > > > > > >> Cc: bhelgaas@google.com; jingoohan1@gmail.com > > > > > >> Subject: Re: [PATCH 1/3] PCI: designware: add accessors for write > > >> permission > > > > > >> of DBI read-only registers > > > > > >> > > > > > >> > > > > > >> Hi Zhiqiang, > > > > > >> > > > > > >> =C3=80s 7:33 AM de 7/6/2017, Zhiqiang Hou escreveu: > > > > > >>> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > > >>> > > > > > >>> The read-only DBI registers can be written over the DBI when set = the > > > > > >>> "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of the > > > > > >>> MISC_CONTROL_1_OFF register. > > > > > >> > > > > > >> I would suggest you to add a cover-letter next time to explain = the > > >> global > > > > > >> picture of the patch-set. > > > > > > > > > > > > Thanks, I will. > > > > > > > > > > > >> > > > > > >> I understand your need for this patch, but I don't agree on the > approach. > > > > > > > > > > > > In the DWC common code, there is a function write a DBI read-only > register > > 'Device class code', and the first 2 patches is to fix it. > > > > > > The 3rd patch is to refactor the Layerscape PCIe driver's = host_init > function > > and reuse the new added accessors. > > > > > > > > > > > >> Sometimes the people in charge of the hardware design / > > >> configuration, forget > > > > > >> to specify the device class and that can be problematic for some > > >> drivers, and > > > > > >> so the typical workaround is to set it in the driver using a = quirk > for example. > > > > > >> > > > > > >> You can see some examples here: > > > > > >> = https://urldefense.proofpoint.com/v2/url?u=3Dhttps-3A__git.kernel.org_p > > >> = ub_scm_linux_kernel_git_torvalds_linux.git_tree_drivers_&d=3DDwIGaQ&c=3DD= > > >> > > PL6_X_6JkXFx7AXWqB0tg&r=3Ds2fO0hii0OGNOv9qQy_HRXy-xAJUD1NNoEcc3io > > _kx0&m > > >> > > =3D0DrBCvOc_J7LaMXBei1qCXxxfbLxWaVErKZ6Rkm6bUc&s=3DsOEmExQFqrCEmpA > > x9LjSeK > > >> RvkW1D-W82ckX5WGCgFWw&e=3D > > > > > >> pci/quirks.c > > > > > > > > > > > > I don't know the PCI quirks, do you mean remove the pci Device = Class > fix > > code from the DWC common code and add it to quirks? > > > > > > > In my opinion adding fixes to a common code is not a good approach. = I > would > > suggest the fix to go into the quirks file. Your answer should be added to here. Then, it will help other people follow this email thread. Best regards, Jingoo Han > > > > @Bjorn: The quirks file is the best place for this type of fixes = right? >=20 > Thanks, > Zhiqiang >=20 ^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers 2017-07-17 19:41 ` Jingoo Han @ 2017-07-18 3:00 ` Z.q. Hou 0 siblings, 0 replies; 13+ messages in thread From: Z.q. Hou @ 2017-07-18 3:00 UTC (permalink / raw) To: Jingoo Han, 'Joao Pinto', linux-pci@vger.kernel.org, bhelgaas@google.com SGkgSmluZ29vIEhhbiwNCg0KVGhhbmtzIGZvciB5b3VyIGNvbW1lbnRzIQ0KDQo+IC0tLS0tT3Jp Z2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IEppbmdvbyBIYW4gW21haWx0bzpqaW5nb29oYW4x QGdtYWlsLmNvbV0NCj4gU2VudDogMjAxN+W5tDfmnIgxOOaXpSAzOjQxDQo+IFRvOiBaLnEuIEhv dSA8emhpcWlhbmcuaG91QG54cC5jb20+OyAnSm9hbyBQaW50bycNCj4gPEpvYW8uUGludG9Ac3lu b3BzeXMuY29tPjsgbGludXgtcGNpQHZnZXIua2VybmVsLm9yZzsNCj4gYmhlbGdhYXNAZ29vZ2xl LmNvbQ0KPiBTdWJqZWN0OiBSZTogW1BBVENIIDEvM10gUENJOiBkZXNpZ253YXJlOiBhZGQgYWNj ZXNzb3JzIGZvciB3cml0ZSBwZXJtaXNzaW9uDQo+IG9mIERCSSByZWFkLW9ubHkgcmVnaXN0ZXJz DQo+IA0KPiBPbiBUdWVzZGF5LCBKdWx5IDExLCAyMDE3IDEyOjExIEFNLCBaLnEuIEhvdSB3cm90 ZToNCj4gPg0KPiA+IEhpIEJqb3JuLA0KPiA+DQo+ID4gRHVlIHRvIGFsbCBGcmVlc2NhbGUgTGF5 ZXJzY3BlIFBDSWUgY29udHJvbGxlcnMgaGF2ZSB0byBmaXggdGhlIENsYXNzDQo+ID4gY29kZSwg YW5kIHRoaXMgZml4dXAgZXhpc3RlZCBpbiBib3RoIExheWVyc2NhcGUgcGNpZSBkcml2ZXIgYW5k IERXQw0KPiA+IGNvbW1vbiBjb2RlLCBzbyBJIHdhbnQgdG8gcmV1c2UgdGhlIGZpeHVwIGluIERX QyBjb21tb24gY29kZS4NCj4gPiBDYW4geW91IGdpdmUgbWUgYW55IHN1Z2dlc3Rpb24/DQo+IA0K PiBQbGVhc2UgZG9uJ3QgYWRkIHlvdXIgY29tbWVudCBvbiB0b3Agb2YgdGhlIGVtYWlsLg0KDQpP aywgZ290IGl0Lg0KDQo+IA0KPiANCj4gPg0KPiA+ID4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0t LS0NCj4gPiA+IEZyb206IEpvYW8gUGludG8gW21haWx0bzpKb2FvLlBpbnRvQHN5bm9wc3lzLmNv bV0NCj4gPiA+IFNlbnQ6IDIwMTflubQ35pyIN+aXpSAxNjo1Mw0KPiA+ID4gVG86IFoucS4gSG91 IDx6aGlxaWFuZy5ob3VAbnhwLmNvbT47IEpvYW8gUGludG8NCj4gPiA+IDxKb2FvLlBpbnRvQHN5 bm9wc3lzLmNvbT47IGxpbnV4LXBjaUB2Z2VyLmtlcm5lbC5vcmc7DQo+ID4gPiBiaGVsZ2Fhc0Bn b29nbGUuY29tDQo+ID4gPiBDYzogamluZ29vaGFuMUBnbWFpbC5jb20NCj4gPiA+IFN1YmplY3Q6 IFJlOiBbUEFUQ0ggMS8zXSBQQ0k6IGRlc2lnbndhcmU6IGFkZCBhY2Nlc3NvcnMgZm9yIHdyaXRl DQo+ID4gcGVybWlzc2lvbg0KPiA+ID4gb2YgREJJIHJlYWQtb25seSByZWdpc3RlcnMNCj4gPiA+ DQo+ID4gPg0KPiA+ID4gSGkgWmhpcWlhbmcsDQo+ID4gPg0KPiA+ID4gw4BzIDQ6NDggQU0gZGUg Ny83LzIwMTcsIFoucS4gSG91IGVzY3JldmV1Og0KPiA+ID4gPiBIaSBKb2FvLA0KPiA+ID4gPg0K PiA+ID4gPg0KPiA+ID4gPg0KPiA+ID4gPiBUaGFua3MgYSBsb3QgZm9yIHlvdXIgY29tbWVudHMh DQo+ID4gPiA+DQo+ID4gPiA+DQo+ID4gPiA+DQo+ID4gPiA+PiAtLS0tLU9yaWdpbmFsIE1lc3Nh Z2UtLS0tLQ0KPiA+ID4gPg0KPiA+ID4gPj4gRnJvbTogSm9hbyBQaW50byBbbWFpbHRvOkpvYW8u UGludG9Ac3lub3BzeXMuY29tXQ0KPiA+ID4gPg0KPiA+ID4gPj4gU2VudDogMjAxN+W5tDfmnIg2 5pelIDE3OjQ0DQo+ID4gPiA+DQo+ID4gPiA+PiBUbzogWi5xLiBIb3UgPHpoaXFpYW5nLmhvdUBu eHAuY29tPjsgbGludXgtcGNpQHZnZXIua2VybmVsLm9yZzsNCj4gPiA+ID4NCj4gPiA+ID4+IEpv YW8uUGludG9Ac3lub3BzeXMuY29tDQo+ID4gPiA+DQo+ID4gPiA+PiBDYzogYmhlbGdhYXNAZ29v Z2xlLmNvbTsgamluZ29vaGFuMUBnbWFpbC5jb20NCj4gPiA+ID4NCj4gPiA+ID4+IFN1YmplY3Q6 IFJlOiBbUEFUQ0ggMS8zXSBQQ0k6IGRlc2lnbndhcmU6IGFkZCBhY2Nlc3NvcnMgZm9yIHdyaXRl DQo+ID4gPiA+PiBwZXJtaXNzaW9uDQo+ID4gPiA+DQo+ID4gPiA+PiBvZiBEQkkgcmVhZC1vbmx5 IHJlZ2lzdGVycw0KPiA+ID4gPg0KPiA+ID4gPj4NCj4gPiA+ID4NCj4gPiA+ID4+DQo+ID4gPiA+ DQo+ID4gPiA+PiBIaSBaaGlxaWFuZywNCj4gPiA+ID4NCj4gPiA+ID4+DQo+ID4gPiA+DQo+ID4g PiA+PiDDgHMgNzozMyBBTSBkZSA3LzYvMjAxNywgWmhpcWlhbmcgSG91IGVzY3JldmV1Og0KPiA+ ID4gPg0KPiA+ID4gPj4+IEZyb206IEhvdSBaaGlxaWFuZyA8WmhpcWlhbmcuSG91QG54cC5jb20+ DQo+ID4gPiA+DQo+ID4gPiA+Pj4NCj4gPiA+ID4NCj4gPiA+ID4+PiBUaGUgcmVhZC1vbmx5IERC SSByZWdpc3RlcnMgY2FuIGJlIHdyaXR0ZW4gb3ZlciB0aGUgREJJIHdoZW4gc2V0DQo+ID4gPiA+ Pj4gdGhlDQo+ID4gPiA+DQo+ID4gPiA+Pj4gIldyaXRlIHRvIFJPIFJlZ2lzdGVycyBVc2luZyBE QkkiIChEQklfUk9fV1JfRU4pIGZpZWxkIG9mIHRoZQ0KPiA+ID4gPg0KPiA+ID4gPj4+IE1JU0Nf Q09OVFJPTF8xX09GRiByZWdpc3Rlci4NCj4gPiA+ID4NCj4gPiA+ID4+DQo+ID4gPiA+DQo+ID4g PiA+PiBJIHdvdWxkIHN1Z2dlc3QgeW91IHRvIGFkZCBhIGNvdmVyLWxldHRlciBuZXh0IHRpbWUg dG8gZXhwbGFpbg0KPiA+ID4gPj4gdGhlIGdsb2JhbA0KPiA+ID4gPg0KPiA+ID4gPj4gcGljdHVy ZSBvZiB0aGUgcGF0Y2gtc2V0Lg0KPiA+ID4gPg0KPiA+ID4gPg0KPiA+ID4gPg0KPiA+ID4gPiBU aGFua3MsIEkgd2lsbC4NCj4gPiA+ID4NCj4gPiA+ID4NCj4gPiA+ID4NCj4gPiA+ID4+DQo+ID4g PiA+DQo+ID4gPiA+PiBJIHVuZGVyc3RhbmQgeW91ciBuZWVkIGZvciB0aGlzIHBhdGNoLCBidXQg SSBkb24ndCBhZ3JlZSBvbiB0aGUNCj4gPiBhcHByb2FjaC4NCj4gPiA+ID4NCj4gPiA+ID4NCj4g PiA+ID4NCj4gPiA+ID4gSW4gdGhlIERXQyBjb21tb24gY29kZSwgdGhlcmUgaXMgYSBmdW5jdGlv biB3cml0ZSBhIERCSSByZWFkLW9ubHkNCj4gPiByZWdpc3Rlcg0KPiA+ID4gJ0RldmljZSBjbGFz cyBjb2RlJywgYW5kIHRoZSBmaXJzdCAyIHBhdGNoZXMgaXMgdG8gZml4IGl0Lg0KPiA+ID4gPg0K PiA+ID4gPiBUaGUgM3JkIHBhdGNoIGlzIHRvIHJlZmFjdG9yIHRoZSBMYXllcnNjYXBlIFBDSWUg ZHJpdmVyJ3MNCj4gPiA+ID4gaG9zdF9pbml0DQo+ID4gZnVuY3Rpb24NCj4gPiA+IGFuZCByZXVz ZSB0aGUgbmV3IGFkZGVkIGFjY2Vzc29ycy4NCj4gPiA+ID4NCj4gPiA+ID4NCj4gPiA+ID4NCj4g PiA+ID4+IFNvbWV0aW1lcyB0aGUgcGVvcGxlIGluIGNoYXJnZSBvZiB0aGUgaGFyZHdhcmUgZGVz aWduIC8NCj4gPiA+ID4+IGNvbmZpZ3VyYXRpb24sIGZvcmdldA0KPiA+ID4gPg0KPiA+ID4gPj4g dG8gc3BlY2lmeSB0aGUgZGV2aWNlIGNsYXNzIGFuZCB0aGF0IGNhbiBiZSBwcm9ibGVtYXRpYyBm b3Igc29tZQ0KPiA+ID4gPj4gZHJpdmVycywgYW5kDQo+ID4gPiA+DQo+ID4gPiA+PiBzbyB0aGUg dHlwaWNhbCB3b3JrYXJvdW5kIGlzIHRvIHNldCBpdCBpbiB0aGUgZHJpdmVyIHVzaW5nIGENCj4g PiA+ID4+IHF1aXJrDQo+ID4gZm9yIGV4YW1wbGUuDQo+ID4gPiA+DQo+ID4gPiA+Pg0KPiA+ID4g Pg0KPiA+ID4gPj4gWW91IGNhbiBzZWUgc29tZSBleGFtcGxlcyBoZXJlOg0KPiA+ID4gPg0KPiA+ ID4gPj4gaHR0cHM6Ly91cmxkZWZlbnNlLnByb29mcG9pbnQuY29tL3YyL3VybD91PWh0dHBzLTNB X19naXQua2VybmVsLm8NCj4gPiA+ID4+IHJnX3ANCj4gPiA+ID4+IHViX3NjbV9saW51eF9rZXJu ZWxfZ2l0X3RvcnZhbGRzX2xpbnV4LmdpdF90cmVlX2RyaXZlcnNfJmQ9RHdJR2FRDQo+ID4gPiA+ PiAmYz1EDQo+ID4gPiA+Pg0KPiA+ID4NCj4gUEw2X1hfNkprWEZ4N0FYV3FCMHRnJnI9czJmTzBo aWkwT0dOT3Y5cVF5X0hSWHkteEFKVUQxTk5vRWNjM2lvDQo+ID4gPiBfa3gwJm0NCj4gPiA+ID4+ DQo+ID4gPg0KPiA9MERyQkN2T2NfSjdMYU1YQmVpMXFDWHh4ZmJMeFdhVkVyS1o2UmttNmJVYyZz PXNPRW1FeFFGcXJDRW1wQQ0KPiA+ID4geDlMalNlSw0KPiA+ID4gPj4gUnZrVzFELVc4MmNrWDVX R0NnRld3JmU9DQo+ID4gPiA+DQo+ID4gPiA+PiBwY2kvcXVpcmtzLmMNCj4gPiA+ID4NCj4gPiA+ ID4NCj4gPiA+ID4NCj4gPiA+ID4gSSBkb24ndCBrbm93IHRoZSBQQ0kgcXVpcmtzLCBkbyB5b3Ug bWVhbiByZW1vdmUgdGhlIHBjaSBEZXZpY2UNCj4gPiA+ID4gQ2xhc3MNCj4gPiBmaXgNCj4gPiA+ IGNvZGUgZnJvbSB0aGUgRFdDIGNvbW1vbiBjb2RlIGFuZCBhZGQgaXQgdG8gcXVpcmtzPw0KPiA+ ID4gPg0KPiA+ID4NCj4gPiA+IEluIG15IG9waW5pb24gYWRkaW5nIGZpeGVzIHRvIGEgY29tbW9u IGNvZGUgaXMgbm90IGEgZ29vZCBhcHByb2FjaC4NCj4gPiA+IEkNCj4gPiB3b3VsZA0KPiA+ID4g c3VnZ2VzdCB0aGUgZml4IHRvIGdvIGludG8gdGhlIHF1aXJrcyBmaWxlLg0KPiANCj4gWW91ciBh bnN3ZXIgc2hvdWxkIGJlIGFkZGVkIHRvIGhlcmUuDQo+IFRoZW4sIGl0IHdpbGwgaGVscCBvdGhl ciBwZW9wbGUgZm9sbG93IHRoaXMgZW1haWwgdGhyZWFkLg0KPiANCg0KWWVzLCBhbmQgZG8geW91 IGtub3cgd2h5IHdyaXRlIHRvIHRoZSBEQkkgcmVhZC1vbmx5IHJlZ2lzdGVyKGNsYXNzIGNvZGUp IHdpdGhvdXQgZW5hYmxlIHRoZSB3cml0ZSBwZXJtaXNzaW9uIG9mIERCSSByZWFkLW9ubHkgcmVn aXN0ZXJzPw0KQ2FuIHlvdSBnaXZlIHNvbWUgc3VnZ2VzdGlvbnM/DQoNClRoYW5rcywNClpoaXFp YW5nDQo= ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers 2017-07-06 9:44 ` [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers Joao Pinto 2017-07-07 3:48 ` Z.q. Hou @ 2017-08-02 21:25 ` Bjorn Helgaas 2017-08-03 3:25 ` Z.q. Hou 1 sibling, 1 reply; 13+ messages in thread From: Bjorn Helgaas @ 2017-08-02 21:25 UTC (permalink / raw) To: Joao Pinto; +Cc: Zhiqiang Hou, linux-pci, bhelgaas, jingoohan1 On Thu, Jul 06, 2017 at 10:44:04AM +0100, Joao Pinto wrote: > > Hi Zhiqiang, > > Às 7:33 AM de 7/6/2017, Zhiqiang Hou escreveu: > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > The read-only DBI registers can be written over the DBI when set > > the "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of the > > MISC_CONTROL_1_OFF register. > > I would suggest you to add a cover-letter next time to explain the global > picture of the patch-set. > > I understand your need for this patch, but I don't agree on the approach. > Sometimes the people in charge of the hardware design / configuration, forget to > specify the device class and that can be problematic for some drivers, and so > the typical workaround is to set it in the driver using a quirk for example. > > You can see some examples here: > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/quirks.c I assume you're suggesting something similar to quirk_tw686x_class() and fixup_ti816x_class(), quirk_amd_nl_class(), quirk_eisa_bridge(), fixup_rev1_53c810(), etc. The current dw_pcie_setup_rc() contains this: /* program correct class for RC */ dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); That suggests that DesignWare-based devices have the wrong class code, and we're trying to fix it. Patch 2/3 of this series suggests that the existing fix doesn't actually work because the register is read-only. If it's necessary and possible to update the class code register in dw_pcie_setup_rc(), I think that's a reasonable spot to do it. The quirks in drivers/pci/quirks.c are necessary because per spec, the PCI Class Code is read-only, so in general we can't update it. In the DesignWare case, the driver has additional device-specific knowledge that allows it to update Class Code value, and I think it makes sense to do it there. > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > --- > > drivers/pci/dwc/pcie-designware.h | 25 +++++++++++++++++++++++++ > > 1 file changed, 25 insertions(+) > > > > diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h > > index b4d2a89..bbdf35b 100644 > > --- a/drivers/pci/dwc/pcie-designware.h > > +++ b/drivers/pci/dwc/pcie-designware.h > > @@ -76,6 +76,9 @@ > > #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) > > #define PCIE_ATU_UPPER_TARGET 0x91C > > > > +#define PCIE_MISC_CONTROL_1_OFF 0x8BC > > +#define PCIE_DBI_RO_WR_EN (0x1 << 0) > > + > > /* > > * iATU Unroll-specific register definitions > > * From 4.80 core version the address translation will be made by unroll > > @@ -279,6 +282,28 @@ static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg) > > return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4); > > } > > > > +static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci) > > +{ > > + u32 reg; > > + u32 val; > > + > > + reg = PCIE_MISC_CONTROL_1_OFF; > > + val = dw_pcie_readl_dbi(pci, reg); > > + val |= PCIE_DBI_RO_WR_EN; > > + dw_pcie_writel_dbi(pci, reg, val); > > +} > > + > > +static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci) > > +{ > > + u32 reg; > > + u32 val; > > + > > + reg = PCIE_MISC_CONTROL_1_OFF; > > + val = dw_pcie_readl_dbi(pci, reg); > > + val &= ~PCIE_DBI_RO_WR_EN; > > + dw_pcie_writel_dbi(pci, reg, val); > > +} > > + > > #ifdef CONFIG_PCIE_DW_HOST > > irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); > > void dw_pcie_msi_init(struct pcie_port *pp); > > > ^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers 2017-08-02 21:25 ` Bjorn Helgaas @ 2017-08-03 3:25 ` Z.q. Hou 0 siblings, 0 replies; 13+ messages in thread From: Z.q. Hou @ 2017-08-03 3:25 UTC (permalink / raw) To: Bjorn Helgaas, Joao Pinto Cc: linux-pci@vger.kernel.org, bhelgaas@google.com, jingoohan1@gmail.com SGkgQmpvcm4sDQoNClRoYW5rcyBhIGxvdCBmb3IgeW91ciBjb21tZW50cyENCg0KPiAtLS0tLU9y aWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9tOiBCam9ybiBIZWxnYWFzIFttYWlsdG86aGVsZ2Fh c0BrZXJuZWwub3JnXQ0KPiBTZW50OiAyMDE35bm0OOaciDPml6UgNToyNQ0KPiBUbzogSm9hbyBQ aW50byA8Sm9hby5QaW50b0BzeW5vcHN5cy5jb20+DQo+IENjOiBaLnEuIEhvdSA8emhpcWlhbmcu aG91QG54cC5jb20+OyBsaW51eC1wY2lAdmdlci5rZXJuZWwub3JnOw0KPiBiaGVsZ2Fhc0Bnb29n bGUuY29tOyBqaW5nb29oYW4xQGdtYWlsLmNvbQ0KPiBTdWJqZWN0OiBSZTogW1BBVENIIDEvM10g UENJOiBkZXNpZ253YXJlOiBhZGQgYWNjZXNzb3JzIGZvciB3cml0ZSBwZXJtaXNzaW9uDQo+IG9m IERCSSByZWFkLW9ubHkgcmVnaXN0ZXJzDQo+IA0KPiBPbiBUaHUsIEp1bCAwNiwgMjAxNyBhdCAx MDo0NDowNEFNICswMTAwLCBKb2FvIFBpbnRvIHdyb3RlOg0KPiA+DQo+ID4gSGkgWmhpcWlhbmcs DQo+ID4NCj4gPiDDgHMgNzozMyBBTSBkZSA3LzYvMjAxNywgWmhpcWlhbmcgSG91IGVzY3JldmV1 Og0KPiA+ID4gRnJvbTogSG91IFpoaXFpYW5nIDxaaGlxaWFuZy5Ib3VAbnhwLmNvbT4NCj4gPiA+ DQo+ID4gPiBUaGUgcmVhZC1vbmx5IERCSSByZWdpc3RlcnMgY2FuIGJlIHdyaXR0ZW4gb3ZlciB0 aGUgREJJIHdoZW4gc2V0IHRoZQ0KPiA+ID4gIldyaXRlIHRvIFJPIFJlZ2lzdGVycyBVc2luZyBE QkkiIChEQklfUk9fV1JfRU4pIGZpZWxkIG9mIHRoZQ0KPiA+ID4gTUlTQ19DT05UUk9MXzFfT0ZG IHJlZ2lzdGVyLg0KPiA+DQo+ID4gSSB3b3VsZCBzdWdnZXN0IHlvdSB0byBhZGQgYSBjb3Zlci1s ZXR0ZXIgbmV4dCB0aW1lIHRvIGV4cGxhaW4gdGhlDQo+ID4gZ2xvYmFsIHBpY3R1cmUgb2YgdGhl IHBhdGNoLXNldC4NCj4gPg0KPiA+IEkgdW5kZXJzdGFuZCB5b3VyIG5lZWQgZm9yIHRoaXMgcGF0 Y2gsIGJ1dCBJIGRvbid0IGFncmVlIG9uIHRoZSBhcHByb2FjaC4NCj4gPiBTb21ldGltZXMgdGhl IHBlb3BsZSBpbiBjaGFyZ2Ugb2YgdGhlIGhhcmR3YXJlIGRlc2lnbiAvIGNvbmZpZ3VyYXRpb24s DQo+ID4gZm9yZ2V0IHRvIHNwZWNpZnkgdGhlIGRldmljZSBjbGFzcyBhbmQgdGhhdCBjYW4gYmUg cHJvYmxlbWF0aWMgZm9yDQo+ID4gc29tZSBkcml2ZXJzLCBhbmQgc28gdGhlIHR5cGljYWwgd29y a2Fyb3VuZCBpcyB0byBzZXQgaXQgaW4gdGhlIGRyaXZlciB1c2luZyBhDQo+IHF1aXJrIGZvciBl eGFtcGxlLg0KPiA+DQo+ID4gWW91IGNhbiBzZWUgc29tZSBleGFtcGxlcyBoZXJlOg0KPiA+IGh0 dHBzOi8vZ2l0Lmtlcm5lbC5vcmcvcHViL3NjbS9saW51eC9rZXJuZWwvZ2l0L3RvcnZhbGRzL2xp bnV4LmdpdC90cmUNCj4gPiBlL2RyaXZlcnMvcGNpL3F1aXJrcy5jDQo+IA0KPiBJIGFzc3VtZSB5 b3UncmUgc3VnZ2VzdGluZyBzb21ldGhpbmcgc2ltaWxhciB0byBxdWlya190dzY4NnhfY2xhc3Mo KSBhbmQNCj4gZml4dXBfdGk4MTZ4X2NsYXNzKCksIHF1aXJrX2FtZF9ubF9jbGFzcygpLCBxdWly a19laXNhX2JyaWRnZSgpLA0KPiBmaXh1cF9yZXYxXzUzYzgxMCgpLCBldGMuDQo+IA0KPiBUaGUg Y3VycmVudCBkd19wY2llX3NldHVwX3JjKCkgY29udGFpbnMgdGhpczoNCj4gDQo+ICAgLyogcHJv Z3JhbSBjb3JyZWN0IGNsYXNzIGZvciBSQyAqLw0KPiAgIGR3X3BjaWVfd3Jfb3duX2NvbmYocHAs IFBDSV9DTEFTU19ERVZJQ0UsIDIsIFBDSV9DTEFTU19CUklER0VfUENJKTsNCj4gDQo+IFRoYXQg c3VnZ2VzdHMgdGhhdCBEZXNpZ25XYXJlLWJhc2VkIGRldmljZXMgaGF2ZSB0aGUgd3JvbmcgY2xh c3MgY29kZSwgYW5kDQo+IHdlJ3JlIHRyeWluZyB0byBmaXggaXQuDQo+IA0KPiBQYXRjaCAyLzMg b2YgdGhpcyBzZXJpZXMgc3VnZ2VzdHMgdGhhdCB0aGUgZXhpc3RpbmcgZml4IGRvZXNuJ3QgYWN0 dWFsbHkgd29yaw0KPiBiZWNhdXNlIHRoZSByZWdpc3RlciBpcyByZWFkLW9ubHkuDQo+IA0KPiBJ ZiBpdCdzIG5lY2Vzc2FyeSBhbmQgcG9zc2libGUgdG8gdXBkYXRlIHRoZSBjbGFzcyBjb2RlIHJl Z2lzdGVyIGluDQo+IGR3X3BjaWVfc2V0dXBfcmMoKSwgSSB0aGluayB0aGF0J3MgYSByZWFzb25h YmxlIHNwb3QgdG8gZG8gaXQuDQo+IA0KPiBUaGUgcXVpcmtzIGluIGRyaXZlcnMvcGNpL3F1aXJr cy5jIGFyZSBuZWNlc3NhcnkgYmVjYXVzZSBwZXIgc3BlYywgdGhlIFBDSSBDbGFzcw0KPiBDb2Rl IGlzIHJlYWQtb25seSwgc28gaW4gZ2VuZXJhbCB3ZSBjYW4ndCB1cGRhdGUgaXQuDQo+IA0KPiBJ biB0aGUgRGVzaWduV2FyZSBjYXNlLCB0aGUgZHJpdmVyIGhhcyBhZGRpdGlvbmFsIGRldmljZS1z cGVjaWZpYyBrbm93bGVkZ2UNCj4gdGhhdCBhbGxvd3MgaXQgdG8gdXBkYXRlIENsYXNzIENvZGUg dmFsdWUsIGFuZCBJIHRoaW5rIGl0IG1ha2VzIHNlbnNlIHRvIGRvIGl0DQo+IHRoZXJlLiANCg0K WWVzLCB3aWxsIGtlZXAgdGhlIENsYXNzIENvZGUgZml4dXAgZnVuY3Rpb24gaW4gdGhlIERlc2ln bldhcmUgZHJpdmVyLg0KDQo+IA0KPiA+ID4gU2lnbmVkLW9mZi1ieTogSG91IFpoaXFpYW5nIDxa aGlxaWFuZy5Ib3VAbnhwLmNvbT4NCj4gPiA+IC0tLQ0KPiA+ID4gIGRyaXZlcnMvcGNpL2R3Yy9w Y2llLWRlc2lnbndhcmUuaCB8IDI1ICsrKysrKysrKysrKysrKysrKysrKysrKysNCj4gPiA+ICAx IGZpbGUgY2hhbmdlZCwgMjUgaW5zZXJ0aW9ucygrKQ0KPiA+ID4NCj4gPiA+IGRpZmYgLS1naXQg YS9kcml2ZXJzL3BjaS9kd2MvcGNpZS1kZXNpZ253YXJlLmgNCj4gPiA+IGIvZHJpdmVycy9wY2kv ZHdjL3BjaWUtZGVzaWdud2FyZS5oDQo+ID4gPiBpbmRleCBiNGQyYTg5Li5iYmRmMzViIDEwMDY0 NA0KPiA+ID4gLS0tIGEvZHJpdmVycy9wY2kvZHdjL3BjaWUtZGVzaWdud2FyZS5oDQo+ID4gPiAr KysgYi9kcml2ZXJzL3BjaS9kd2MvcGNpZS1kZXNpZ253YXJlLmgNCj4gPiA+IEBAIC03Niw2ICs3 Niw5IEBADQo+ID4gPiAgI2RlZmluZSBQQ0lFX0FUVV9GVU5DKHgpCQkoKCh4KSAmIDB4NykgPDwg MTYpDQo+ID4gPiAgI2RlZmluZSBQQ0lFX0FUVV9VUFBFUl9UQVJHRVQJCTB4OTFDDQo+ID4gPg0K PiA+ID4gKyNkZWZpbmUgUENJRV9NSVNDX0NPTlRST0xfMV9PRkYJCTB4OEJDDQo+ID4gPiArI2Rl ZmluZSBQQ0lFX0RCSV9ST19XUl9FTgkJKDB4MSA8PCAwKQ0KPiA+ID4gKw0KPiA+ID4gIC8qDQo+ ID4gPiAgICogaUFUVSBVbnJvbGwtc3BlY2lmaWMgcmVnaXN0ZXIgZGVmaW5pdGlvbnMNCj4gPiA+ ICAgKiBGcm9tIDQuODAgY29yZSB2ZXJzaW9uIHRoZSBhZGRyZXNzIHRyYW5zbGF0aW9uIHdpbGwg YmUgbWFkZSBieQ0KPiA+ID4gdW5yb2xsIEBAIC0yNzksNiArMjgyLDI4IEBAIHN0YXRpYyBpbmxp bmUgdTMyIGR3X3BjaWVfcmVhZGxfZGJpMihzdHJ1Y3QNCj4gZHdfcGNpZSAqcGNpLCB1MzIgcmVn KQ0KPiA+ID4gIAlyZXR1cm4gX19kd19wY2llX3JlYWRfZGJpKHBjaSwgcGNpLT5kYmlfYmFzZTIs IHJlZywgMHg0KTsgIH0NCj4gPiA+DQo+ID4gPiArc3RhdGljIGlubGluZSB2b2lkIGR3X3BjaWVf ZGJpX3JvX3dyX2VuKHN0cnVjdCBkd19wY2llICpwY2kpIHsNCj4gPiA+ICsJdTMyIHJlZzsNCj4g PiA+ICsJdTMyIHZhbDsNCj4gPiA+ICsNCj4gPiA+ICsJcmVnID0gUENJRV9NSVNDX0NPTlRST0xf MV9PRkY7DQo+ID4gPiArCXZhbCA9IGR3X3BjaWVfcmVhZGxfZGJpKHBjaSwgcmVnKTsNCj4gPiA+ ICsJdmFsIHw9IFBDSUVfREJJX1JPX1dSX0VOOw0KPiA+ID4gKwlkd19wY2llX3dyaXRlbF9kYmko cGNpLCByZWcsIHZhbCk7IH0NCj4gPiA+ICsNCj4gPiA+ICtzdGF0aWMgaW5saW5lIHZvaWQgZHdf cGNpZV9kYmlfcm9fd3JfZGlzKHN0cnVjdCBkd19wY2llICpwY2kpIHsNCj4gPiA+ICsJdTMyIHJl ZzsNCj4gPiA+ICsJdTMyIHZhbDsNCj4gPiA+ICsNCj4gPiA+ICsJcmVnID0gUENJRV9NSVNDX0NP TlRST0xfMV9PRkY7DQo+ID4gPiArCXZhbCA9IGR3X3BjaWVfcmVhZGxfZGJpKHBjaSwgcmVnKTsN Cj4gPiA+ICsJdmFsICY9IH5QQ0lFX0RCSV9ST19XUl9FTjsNCj4gPiA+ICsJZHdfcGNpZV93cml0 ZWxfZGJpKHBjaSwgcmVnLCB2YWwpOyB9DQo+ID4gPiArDQo+ID4gPiAgI2lmZGVmIENPTkZJR19Q Q0lFX0RXX0hPU1QNCj4gPiA+ICBpcnFyZXR1cm5fdCBkd19oYW5kbGVfbXNpX2lycShzdHJ1Y3Qg cGNpZV9wb3J0ICpwcCk7ICB2b2lkDQo+ID4gPiBkd19wY2llX21zaV9pbml0KHN0cnVjdCBwY2ll X3BvcnQgKnBwKTsNCj4gPiA+DQo+ID4NCg0KVGhhbmtzLA0KWmhpcWlhbmcNCg== ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2017-08-03 3:25 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-07-06 6:33 [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers Zhiqiang Hou 2017-07-06 6:33 ` [PATCH 2/3] PCI: designware: enable write permission before updating class code Zhiqiang Hou 2017-07-06 6:33 ` [PATCH 3/3] PCI: layerscape: refactor the host_init function Zhiqiang Hou 2017-08-02 21:11 ` Bjorn Helgaas 2017-08-03 3:17 ` Z.q. Hou 2017-07-06 9:44 ` [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers Joao Pinto 2017-07-07 3:48 ` Z.q. Hou 2017-07-07 8:53 ` Joao Pinto 2017-07-11 4:11 ` Z.q. Hou 2017-07-17 19:41 ` Jingoo Han 2017-07-18 3:00 ` Z.q. Hou 2017-08-02 21:25 ` Bjorn Helgaas 2017-08-03 3:25 ` Z.q. Hou
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).