From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
To: <linux-pci@vger.kernel.org>, <bhelgaas@google.com>,
<jingoohan1@gmail.com>, <Joao.Pinto@synopsys.com>
Cc: <minghuan.lian@nxp.com>, <mingkai.hu@nxp.com>, <roy.zang@nxp.com>,
Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Subject: [PATCHv2 2/6] PCI: designware: enable write permission before updating class code
Date: Thu, 3 Aug 2017 16:23:36 +0800 [thread overview]
Message-ID: <1501748620-42866-3-git-send-email-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <1501748620-42866-1-git-send-email-Zhiqiang.Hou@nxp.com>
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
The existing fix doesn't actually work because the Class register is
read-only, so it must enable the write permission before write the
correct value to this register.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
- None
drivers/pci/dwc/pcie-designware-host.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index d29c020..6e10cda 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -634,8 +634,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
+ /* Enable write permission for the DBI read-only register */
+ dw_pcie_dbi_ro_wr_en(pci);
/* program correct class for RC */
dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
+ /* Better disable write permission right after the update */
+ dw_pcie_dbi_ro_wr_dis(pci);
dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
val |= PORT_LOGIC_SPEED_CHANGE;
--
2.1.0.27.g96db324
next prev parent reply other threads:[~2017-08-03 8:40 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-03 8:23 [PATCHv2 0/6] PCI: fix the designware Class code fixup doesn't work issue and refactor ls-pcie host init Zhiqiang Hou
2017-08-03 8:23 ` [PATCHv2 1/6] PCI: designware: add accessors for write permission of DBI read-only registers Zhiqiang Hou
2017-08-08 12:45 ` Joao Pinto
2017-08-09 2:50 ` Z.q. Hou
2017-08-03 8:23 ` Zhiqiang Hou [this message]
2017-08-08 12:45 ` [PATCHv2 2/6] PCI: designware: enable write permission before updating class code Joao Pinto
2017-08-09 2:51 ` Z.q. Hou
2017-08-03 8:23 ` [PATCHv2 3/6] PCI: layerscape: use accessors to enable/disable DBI RO registers' write permission Zhiqiang Hou
2017-08-08 12:46 ` Joao Pinto
2017-08-09 2:52 ` Z.q. Hou
2017-08-03 8:23 ` [PATCHv2 4/6] PCI: layerscape: refactor the host_init function Zhiqiang Hou
2017-08-08 13:13 ` Joao Pinto
2017-08-09 2:53 ` Z.q. Hou
2017-08-14 21:38 ` Bjorn Helgaas
2017-08-14 22:26 ` Bjorn Helgaas
2017-08-15 3:21 ` Z.q. Hou
2017-08-15 9:34 ` Stanimir Varbanov
2017-08-16 5:19 ` Z.q. Hou
2017-08-15 3:05 ` Z.q. Hou
2017-08-03 8:23 ` [PATCHv2 5/6] PCI: layerscape: Disable the outbound windows configured by bootloader Zhiqiang Hou
2017-08-03 8:23 ` [PATCHv2 6/6] PCI: layerscape: remove the duplicate Class field fix code Zhiqiang Hou
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