From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
To: <linux-pci@vger.kernel.org>, <bhelgaas@google.com>,
<jingoohan1@gmail.com>, <Joao.Pinto@synopsys.com>
Cc: <minghuan.lian@nxp.com>, <mingkai.hu@nxp.com>, <roy.zang@nxp.com>,
<svarbanov@mm-sol.com>, <niklas.cassel@axis.com>,
<jesper.nilsson@axis.com>, Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Subject: [PATCHv3 5/9] PCI: layerscape: Disable the outbound windows configured by bootloader
Date: Wed, 16 Aug 2017 12:56:55 +0800 [thread overview]
Message-ID: <1502859419-33696-6-git-send-email-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <1502859419-33696-1-git-send-email-Zhiqiang.Hou@nxp.com>
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Disable all the outbound windows to avoid one transaction hitting
multiple outbound windows, because the function dw_pcie_setup_rc
will re-configure the outbound windows which maybe confict with
the bootloader configured.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
- No change
drivers/pci/dwc/pci-layerscape.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 57b86a0..44a603d 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -35,6 +35,8 @@
#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
+#define PCIE_IATU_NUM 6
+
struct ls_pcie_drvdata {
u32 lut_offset;
u32 ltssm_shift;
@@ -91,6 +93,14 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
}
+static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie)
+{
+ int i;
+
+ for (i = 0; i < PCIE_IATU_NUM; i++)
+ dw_pcie_disable_atu(pcie->pci, DW_PCIE_REGION_OUTBOUND, i);
+}
+
static int ls1021_pcie_link_up(struct dw_pcie *pci)
{
u32 state;
@@ -128,6 +138,13 @@ static int ls_pcie_host_init(struct pcie_port *pp)
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct ls_pcie *pcie = to_ls_pcie(pci);
+ /*
+ * Disable the outbound windows configured by bootloader to avoid
+ * one transaction hitting multiple outbound windows and the function
+ * dw_pcie_setup_rc will re-configure the outbound windows.
+ */
+ ls_pcie_disable_outbound_atus(pcie);
+
iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
ls_pcie_fix_class(pcie);
ls_pcie_clear_multifunction(pcie);
--
2.1.0.27.g96db324
next prev parent reply other threads:[~2017-08-16 5:14 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-16 4:56 [PATCHv3 0/9] PCI: dwc: refactor ls-pcie ->host_init() and fix bug for dw_pcie_setup_rc Zhiqiang Hou
2017-08-16 4:56 ` [PATCHv3 1/9] PCI: layerscape: Add dw_pcie_setup_rc to ls-pcie common host init Zhiqiang Hou
2017-08-16 4:56 ` [PATCHv3 2/9] PCI: layerscape: move STRFMR1 access out from the DBI write-enable bracket Zhiqiang Hou
2017-08-16 4:56 ` [PATCHv3 3/9] PCI: layerscape: add class code and multifunction fixups for ls1021a Zhiqiang Hou
2017-08-16 4:56 ` [PATCHv3 4/9] PCI: layerscape: refactor the host_init function Zhiqiang Hou
2017-08-16 4:56 ` Zhiqiang Hou [this message]
2017-08-16 4:56 ` [PATCHv3 6/9] PCI: designware: add accessors for write permission of DBI read-only registers Zhiqiang Hou
2017-08-16 11:33 ` Stanimir Varbanov
2017-08-17 3:03 ` Z.q. Hou
2017-08-17 11:25 ` Stanimir Varbanov
2017-08-18 5:28 ` Z.q. Hou
2017-08-18 11:51 ` Joao Pinto
2017-08-21 3:21 ` Z.q. Hou
2017-08-16 4:56 ` [PATCHv3 7/9] PCI: layerscape: use accessors to enable/disable DBI RO registers' write permission Zhiqiang Hou
2017-08-16 4:56 ` [PATCHv3 8/9] PCI: designware: enable write permission before updating DBI RO registers Zhiqiang Hou
2017-08-16 4:56 ` [PATCHv3 9/9] PCI: dwc: remove the obsolete fixups Zhiqiang Hou
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