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From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
To: <linux-pci@vger.kernel.org>, <bhelgaas@google.com>,
	<jingoohan1@gmail.com>, <Joao.Pinto@synopsys.com>
Cc: <minghuan.lian@nxp.com>, <mingkai.hu@nxp.com>, <roy.zang@nxp.com>,
	<svarbanov@mm-sol.com>, <niklas.cassel@axis.com>,
	<jesper.nilsson@axis.com>, Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Subject: [PATCHv3 7/9] PCI: layerscape: use accessors to enable/disable DBI RO registers' write permission
Date: Wed, 16 Aug 2017 12:56:57 +0800	[thread overview]
Message-ID: <1502859419-33696-8-git-send-email-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <1502859419-33696-1-git-send-email-Zhiqiang.Hou@nxp.com>

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Use the accessors instead accessing the DBI read-only write enable
register directly.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
 - No change

 drivers/pci/dwc/pci-layerscape.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 44a603d..0c1330f 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -33,7 +33,6 @@
 
 /* PEX Internal Configuration Registers */
 #define PCIE_STRFMR1		0x71c /* Symbol Timer & Filter Mask Register1 */
-#define PCIE_DBI_RO_WR_EN	0x8bc /* DBI Read-Only Write Enable Register */
 
 #define PCIE_IATU_NUM		6
 
@@ -145,10 +144,10 @@ static int ls_pcie_host_init(struct pcie_port *pp)
 	 */
 	ls_pcie_disable_outbound_atus(pcie);
 
-	iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
+	dw_pcie_dbi_ro_wr_en(pci);
 	ls_pcie_fix_class(pcie);
 	ls_pcie_clear_multifunction(pcie);
-	iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
+	dw_pcie_dbi_ro_wr_dis(pci);
 
 	ls_pcie_drop_msg_tlp(pcie);
 
-- 
2.1.0.27.g96db324

  parent reply	other threads:[~2017-08-16  5:14 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-16  4:56 [PATCHv3 0/9] PCI: dwc: refactor ls-pcie ->host_init() and fix bug for dw_pcie_setup_rc Zhiqiang Hou
2017-08-16  4:56 ` [PATCHv3 1/9] PCI: layerscape: Add dw_pcie_setup_rc to ls-pcie common host init Zhiqiang Hou
2017-08-16  4:56 ` [PATCHv3 2/9] PCI: layerscape: move STRFMR1 access out from the DBI write-enable bracket Zhiqiang Hou
2017-08-16  4:56 ` [PATCHv3 3/9] PCI: layerscape: add class code and multifunction fixups for ls1021a Zhiqiang Hou
2017-08-16  4:56 ` [PATCHv3 4/9] PCI: layerscape: refactor the host_init function Zhiqiang Hou
2017-08-16  4:56 ` [PATCHv3 5/9] PCI: layerscape: Disable the outbound windows configured by bootloader Zhiqiang Hou
2017-08-16  4:56 ` [PATCHv3 6/9] PCI: designware: add accessors for write permission of DBI read-only registers Zhiqiang Hou
2017-08-16 11:33   ` Stanimir Varbanov
2017-08-17  3:03     ` Z.q. Hou
2017-08-17 11:25       ` Stanimir Varbanov
2017-08-18  5:28         ` Z.q. Hou
2017-08-18 11:51       ` Joao Pinto
2017-08-21  3:21         ` Z.q. Hou
2017-08-16  4:56 ` Zhiqiang Hou [this message]
2017-08-16  4:56 ` [PATCHv3 8/9] PCI: designware: enable write permission before updating DBI RO registers Zhiqiang Hou
2017-08-16  4:56 ` [PATCHv3 9/9] PCI: dwc: remove the obsolete fixups Zhiqiang Hou

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