From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sn1nam01on0067.outbound.protection.outlook.com ([104.47.32.67]:39183 "EHLO NAM01-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750912AbdHPFOW (ORCPT ); Wed, 16 Aug 2017 01:14:22 -0400 From: Zhiqiang Hou To: , , , CC: , , , , , , Hou Zhiqiang Subject: [PATCHv3 8/9] PCI: designware: enable write permission before updating DBI RO registers Date: Wed, 16 Aug 2017 12:56:58 +0800 Message-ID: <1502859419-33696-9-git-send-email-Zhiqiang.Hou@nxp.com> In-Reply-To: <1502859419-33696-1-git-send-email-Zhiqiang.Hou@nxp.com> References: <1502859419-33696-1-git-send-email-Zhiqiang.Hou@nxp.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-pci-owner@vger.kernel.org List-ID: From: Hou Zhiqiang The existing fix doesn't actually work because the Class register and interrupt PIN register are read-only, so it must enable the write permission before writing the correct value to these registers. Signed-off-by: Hou Zhiqiang --- V3: - Add the same fixup for interrupt pin code. drivers/pci/dwc/pcie-designware-host.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c index 1576211..582f5cc 100644 --- a/drivers/pci/dwc/pcie-designware-host.c +++ b/drivers/pci/dwc/pcie-designware-host.c @@ -597,10 +597,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); /* setup interrupt pins */ + dw_pcie_dbi_ro_wr_en(pci); val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); val &= 0xffff00ff; val |= 0x00000100; dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); + dw_pcie_dbi_ro_wr_dis(pci); /* setup bus numbers */ val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); @@ -637,8 +639,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); + /* Enable write permission for the DBI read-only register */ + dw_pcie_dbi_ro_wr_en(pci); /* program correct class for RC */ dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); + /* Better disable write permission right after the update */ + dw_pcie_dbi_ro_wr_dis(pci); dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); val |= PORT_LOGIC_SPEED_CHANGE; -- 2.1.0.27.g96db324