[PATCHv3 0/9] PCI: dwc: refactor ls-pcie ->host_init() and fix bug for dw_pcie_setup_rc

[PATCHv3 0/9] PCI: dwc: refactor ls-pcie ->host_init() and fix bug for dw_pcie_setup_rc

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Reordered and reformed the version 2 patch set:
The first 5 patches are used to refactor the ls-pcie host init function
and make it robust. And make ls1021a pcie reuse the ls-pcie common host
init function. Disable the bootloader configured outbound windows to avoid
conflict to outbound windows configured by dw_pcie_setup_rc().

The rest 4 patches are aim to fix the designware Class code and interrupt
Pin code fixup doesn't work issue, because they are DBI read-only registers,
so must enable the write permission before updating this register. And removed
the obsolete fixups from layerscape, qcom and artpec6 pcie drivers.

Hou Zhiqiang (9):
  PCI: layerscape: Add dw_pcie_setup_rc to ls-pcie common host init
  PCI: layerscape: move STRFMR1 access out from the DBI write-enable
    bracket
  PCI: layerscape: add class code and multifunction fixups for ls1021a
  PCI: layerscape: refactor the host_init function
  PCI: layerscape: Disable the outbound windows configured by bootloader
  PCI: designware: add accessors for write permission of DBI read-only
    registers
  PCI: layerscape: use accessors to enable/disable DBI RO registers'
    write permission
  PCI: designware: enable write permission before updating DBI RO
    registers
  PCI: dwc: remove the obsolete fixups

 drivers/pci/dwc/pci-layerscape.c       | 90 ++++++++++++++++++----------------
 drivers/pci/dwc/pcie-artpec6.c         |  6 ---
 drivers/pci/dwc/pcie-designware-host.c |  6 +++
 drivers/pci/dwc/pcie-designware.h      | 25 ++++++++++
 drivers/pci/dwc/pcie-qcom.c            | 17 -------
 5 files changed, 80 insertions(+), 64 deletions(-)

-- 
2.1.0.27.g96db324

[PATCHv3 1/9] PCI: layerscape: Add dw_pcie_setup_rc to ls-pcie common host init

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

This function has been added to ls1021a host init function, but lost to
add to layerscape common host init, so other platforms still use the
setups from bootloader.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
 - New patch separated from 4/6 patch set v2.

 drivers/pci/dwc/pci-layerscape.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 7581490..aebefb4 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -165,6 +165,8 @@ static int ls_pcie_host_init(struct pcie_port *pp)
 	ls_pcie_drop_msg_tlp(pcie);
 	iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
 
+	dw_pcie_setup_rc(pp);
+
 	return 0;
 }
 
-- 
2.1.0.27.g96db324

[PATCHv3 2/9] PCI: layerscape: move STRFMR1 access out from the DBI write-enable bracket

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The STRFMR1 is not a DBI read-only register, so move it out from the
write-enable bracket.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
 - New patch separated from 3/6 patch set v2.

 drivers/pci/dwc/pci-layerscape.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index aebefb4..c169400 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -162,9 +162,10 @@ static int ls_pcie_host_init(struct pcie_port *pp)
 	iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
 	ls_pcie_fix_class(pcie);
 	ls_pcie_clear_multifunction(pcie);
-	ls_pcie_drop_msg_tlp(pcie);
 	iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
 
+	ls_pcie_drop_msg_tlp(pcie);
+
 	dw_pcie_setup_rc(pp);
 
 	return 0;
-- 
2.1.0.27.g96db324

[PATCHv3 3/9] PCI: layerscape: add class code and multifunction fixups for ls1021a

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The current code depends on these 2 fixups implemented in bootloader,
this patch is to resolve the dependence.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
 - New patch

 drivers/pci/dwc/pci-layerscape.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index c169400..3aa3421 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -134,6 +134,11 @@ static int ls1021_pcie_host_init(struct pcie_port *pp)
 
 	dw_pcie_setup_rc(pp);
 
+	iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
+	ls_pcie_fix_class(pcie);
+	ls_pcie_clear_multifunction(pcie);
+	iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
+
 	ls_pcie_drop_msg_tlp(pcie);
 
 	return 0;
-- 
2.1.0.27.g96db324

[PATCHv3 4/9] PCI: layerscape: refactor the host_init function

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Make the ls1021a's host_init reuse layerscape platform's common
host_init function.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
 - Separate the calling of dw_pcie_setup_rc() to 1/9 of this patch set.

 drivers/pci/dwc/pci-layerscape.c | 65 ++++++++++++++++++----------------------
 1 file changed, 29 insertions(+), 36 deletions(-)

diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 3aa3421..57b86a0 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -108,42 +108,6 @@ static int ls1021_pcie_link_up(struct dw_pcie *pci)
 	return 1;
 }
 
-static int ls1021_pcie_host_init(struct pcie_port *pp)
-{
-	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
-	struct ls_pcie *pcie = to_ls_pcie(pci);
-	struct device *dev = pci->dev;
-	u32 index[2];
-	int ret;
-
-	pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
-						     "fsl,pcie-scfg");
-	if (IS_ERR(pcie->scfg)) {
-		ret = PTR_ERR(pcie->scfg);
-		dev_err(dev, "No syscfg phandle specified\n");
-		pcie->scfg = NULL;
-		return ret;
-	}
-
-	if (of_property_read_u32_array(dev->of_node,
-				       "fsl,pcie-scfg", index, 2)) {
-		pcie->scfg = NULL;
-		return -EINVAL;
-	}
-	pcie->index = index[1];
-
-	dw_pcie_setup_rc(pp);
-
-	iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
-	ls_pcie_fix_class(pcie);
-	ls_pcie_clear_multifunction(pcie);
-	iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
-
-	ls_pcie_drop_msg_tlp(pcie);
-
-	return 0;
-}
-
 static int ls_pcie_link_up(struct dw_pcie *pci)
 {
 	struct ls_pcie *pcie = to_ls_pcie(pci);
@@ -176,6 +140,35 @@ static int ls_pcie_host_init(struct pcie_port *pp)
 	return 0;
 }
 
+static int ls1021_pcie_host_init(struct pcie_port *pp)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+	struct ls_pcie *pcie = to_ls_pcie(pci);
+	struct device *dev = pci->dev;
+	u32 index[2];
+	int ret;
+
+	pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
+						     "fsl,pcie-scfg");
+	if (IS_ERR(pcie->scfg)) {
+		ret = PTR_ERR(pcie->scfg);
+		dev_err(dev, "No syscfg phandle specified\n");
+		pcie->scfg = NULL;
+		return ret;
+	}
+
+	if (of_property_read_u32_array(dev->of_node,
+				       "fsl,pcie-scfg", index, 2)) {
+		pcie->scfg = NULL;
+		return -EINVAL;
+	}
+	pcie->index = index[1];
+
+	ls_pcie_host_init(pp);
+
+	return 0;
+}
+
 static int ls_pcie_msi_host_init(struct pcie_port *pp,
 				 struct msi_controller *chip)
 {
-- 
2.1.0.27.g96db324

[PATCHv3 5/9] PCI: layerscape: Disable the outbound windows configured by bootloader

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Disable all the outbound windows to avoid one transaction hitting
multiple outbound windows, because the function dw_pcie_setup_rc
will re-configure the outbound windows which maybe confict with
the bootloader configured.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
 - No change

 drivers/pci/dwc/pci-layerscape.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 57b86a0..44a603d 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -35,6 +35,8 @@
 #define PCIE_STRFMR1		0x71c /* Symbol Timer & Filter Mask Register1 */
 #define PCIE_DBI_RO_WR_EN	0x8bc /* DBI Read-Only Write Enable Register */
 
+#define PCIE_IATU_NUM		6
+
 struct ls_pcie_drvdata {
 	u32 lut_offset;
 	u32 ltssm_shift;
@@ -91,6 +93,14 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
 	iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
 }
 
+static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie)
+{
+	int i;
+
+	for (i = 0; i < PCIE_IATU_NUM; i++)
+		dw_pcie_disable_atu(pcie->pci, DW_PCIE_REGION_OUTBOUND, i);
+}
+
 static int ls1021_pcie_link_up(struct dw_pcie *pci)
 {
 	u32 state;
@@ -128,6 +138,13 @@ static int ls_pcie_host_init(struct pcie_port *pp)
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct ls_pcie *pcie = to_ls_pcie(pci);
 
+	/*
+	 * Disable the outbound windows configured by bootloader to avoid
+	 * one transaction hitting multiple outbound windows and the function
+	 * dw_pcie_setup_rc will re-configure the outbound windows.
+	 */
+	ls_pcie_disable_outbound_atus(pcie);
+
 	iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
 	ls_pcie_fix_class(pcie);
 	ls_pcie_clear_multifunction(pcie);
-- 
2.1.0.27.g96db324

[PATCHv3 6/9] PCI: designware: add accessors for write permission of DBI read-only registers

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The read-only DBI registers can be written over the DBI when set
the "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of the
MISC_CONTROL_1_OFF register.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
 - No change

 drivers/pci/dwc/pcie-designware.h | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index 7366c81..0c5f874 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -76,6 +76,9 @@
 #define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
 #define PCIE_ATU_UPPER_TARGET		0x91C
 
+#define PCIE_MISC_CONTROL_1_OFF		0x8BC
+#define PCIE_DBI_RO_WR_EN		(0x1 << 0)
+
 /*
  * iATU Unroll-specific register definitions
  * From 4.80 core version the address translation will be made by unroll
@@ -279,6 +282,28 @@ static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg)
 	return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4);
 }
 
+static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)
+{
+	u32 reg;
+	u32 val;
+
+	reg = PCIE_MISC_CONTROL_1_OFF;
+	val = dw_pcie_readl_dbi(pci, reg);
+	val |= PCIE_DBI_RO_WR_EN;
+	dw_pcie_writel_dbi(pci, reg, val);
+}
+
+static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
+{
+	u32 reg;
+	u32 val;
+
+	reg = PCIE_MISC_CONTROL_1_OFF;
+	val = dw_pcie_readl_dbi(pci, reg);
+	val &= ~PCIE_DBI_RO_WR_EN;
+	dw_pcie_writel_dbi(pci, reg, val);
+}
+
 #ifdef CONFIG_PCIE_DW_HOST
 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
 void dw_pcie_msi_init(struct pcie_port *pp);
-- 
2.1.0.27.g96db324

Re: [PATCHv3 6/9] PCI: designware: add accessors for write permission of DBI read-only registers

[Stanimir Varbanov]

Hi,

On 08/16/2017 07:56 AM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> The read-only DBI registers can be written over the DBI when set
> the "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of the
> MISC_CONTROL_1_OFF register.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V3:
>  - No change
> 
>  drivers/pci/dwc/pcie-designware.h | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
> index 7366c81..0c5f874 100644
> --- a/drivers/pci/dwc/pcie-designware.h
> +++ b/drivers/pci/dwc/pcie-designware.h
> @@ -76,6 +76,9 @@
>  #define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
>  #define PCIE_ATU_UPPER_TARGET		0x91C
>  
> +#define PCIE_MISC_CONTROL_1_OFF		0x8BC
> +#define PCIE_DBI_RO_WR_EN		(0x1 << 0)

Does those registers exist for dwc version 4.01a?

I managed to test 6/9, 8/9 and 9/9 on qcom platform (apq8064) which has
4.01a version and it doesn't work, i.e. the PCI_CLASS_BRIDGE_PCI is not
returned when read PCI_CLASS_DEVICE offset.

> +
>  /*
>   * iATU Unroll-specific register definitions
>   * From 4.80 core version the address translation will be made by unroll
> @@ -279,6 +282,28 @@ static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg)
>  	return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4);
>  }
>  
> +static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)
> +{
> +	u32 reg;
> +	u32 val;
> +
> +	reg = PCIE_MISC_CONTROL_1_OFF;
> +	val = dw_pcie_readl_dbi(pci, reg);
> +	val |= PCIE_DBI_RO_WR_EN;
> +	dw_pcie_writel_dbi(pci, reg, val);
> +}
> +
> +static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
> +{
> +	u32 reg;
> +	u32 val;
> +
> +	reg = PCIE_MISC_CONTROL_1_OFF;
> +	val = dw_pcie_readl_dbi(pci, reg);
> +	val &= ~PCIE_DBI_RO_WR_EN;
> +	dw_pcie_writel_dbi(pci, reg, val);
> +}
> +
>  #ifdef CONFIG_PCIE_DW_HOST
>  irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
>  void dw_pcie_msi_init(struct pcie_port *pp);
> 

regards,
Stan

RE: [PATCHv3 6/9] PCI: designware: add accessors for write permission of DBI read-only registers

[Z.q. Hou]

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Re: [PATCHv3 6/9] PCI: designware: add accessors for write permission of DBI read-only registers

[Stanimir Varbanov]

Hi,

On 08/17/2017 06:03 AM, Z.q. Hou wrote:
> Hi Stanimir,
> 
> Thanks for your feedback!
> 
>> -----Original Message-----
>> From: Stanimir Varbanov [mailto:svarbanov@mm-sol.com]
>> Sent: 2017年8月16日 19:34
>> To: Z.q. Hou <zhiqiang.hou@nxp.com>; linux-pci@vger.kernel.org;
>> bhelgaas@google.com; jingoohan1@gmail.com; Joao.Pinto@synopsys.com
>> Cc: M.h. Lian <minghuan.lian@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>;
>> Roy Zang <roy.zang@nxp.com>; niklas.cassel@axis.com;
>> jesper.nilsson@axis.com
>> Subject: Re: [PATCHv3 6/9] PCI: designware: add accessors for write
>> permission of DBI read-only registers
>>
>> Hi,
>>
>> On 08/16/2017 07:56 AM, Zhiqiang Hou wrote:
>>> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>>>
>>> The read-only DBI registers can be written over the DBI when set the
>>> "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of the
>>> MISC_CONTROL_1_OFF register.
>>>
>>> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>>> ---
>>> V3:
>>>  - No change
>>>
>>>  drivers/pci/dwc/pcie-designware.h | 25 +++++++++++++++++++++++++
>>>  1 file changed, 25 insertions(+)
>>>
>>> diff --git a/drivers/pci/dwc/pcie-designware.h
>>> b/drivers/pci/dwc/pcie-designware.h
>>> index 7366c81..0c5f874 100644
>>> --- a/drivers/pci/dwc/pcie-designware.h
>>> +++ b/drivers/pci/dwc/pcie-designware.h
>>> @@ -76,6 +76,9 @@
>>>  #define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
>>>  #define PCIE_ATU_UPPER_TARGET		0x91C
>>>
>>> +#define PCIE_MISC_CONTROL_1_OFF		0x8BC
>>> +#define PCIE_DBI_RO_WR_EN		(0x1 << 0)
>>
>> Does those registers exist for dwc version 4.01a?
> 
> Joao, can you help to check this?
> I referred to DesignWare cores PCI Express controller databook version 4.21a.
> The Freescale Layerscape implement does not export the version of designware PCIe controller, I don't know which versions have those registers, if it does not work on qcom platform, I will remove the qcom related changes.

It won't work on two of the supported SoCs so I'd prefer to drop qcom
changes for now.

regards,
Stan

RE: [PATCHv3 6/9] PCI: designware: add accessors for write permission of DBI read-only registers

[Z.q. Hou]

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Re: [PATCHv3 6/9] PCI: designware: add accessors for write permission of DBI read-only registers

[Joao Pinto]

Hi Zhiqiang and Stanimir,

Às 4:03 AM de 8/17/2017, Z.q. Hou escreveu:
> Hi Stanimir,
> 
> Thanks for your feedback!
> 
>> -----Original Message-----
>> From: Stanimir Varbanov [mailto:svarbanov@mm-sol.com]
>> Sent: 2017年8月16日 19:34
>> To: Z.q. Hou <zhiqiang.hou@nxp.com>; linux-pci@vger.kernel.org;
>> bhelgaas@google.com; jingoohan1@gmail.com; Joao.Pinto@synopsys.com
>> Cc: M.h. Lian <minghuan.lian@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>;
>> Roy Zang <roy.zang@nxp.com>; niklas.cassel@axis.com;
>> jesper.nilsson@axis.com
>> Subject: Re: [PATCHv3 6/9] PCI: designware: add accessors for write
>> permission of DBI read-only registers
>>
>> Hi,
>>
>> On 08/16/2017 07:56 AM, Zhiqiang Hou wrote:
>>> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>>>
>>> The read-only DBI registers can be written over the DBI when set the
>>> "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of the
>>> MISC_CONTROL_1_OFF register.
>>>
>>> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>>> ---
>>> V3:
>>>  - No change
>>>
>>>  drivers/pci/dwc/pcie-designware.h | 25 +++++++++++++++++++++++++
>>>  1 file changed, 25 insertions(+)
>>>
>>> diff --git a/drivers/pci/dwc/pcie-designware.h
>>> b/drivers/pci/dwc/pcie-designware.h
>>> index 7366c81..0c5f874 100644
>>> --- a/drivers/pci/dwc/pcie-designware.h
>>> +++ b/drivers/pci/dwc/pcie-designware.h
>>> @@ -76,6 +76,9 @@
>>>  #define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
>>>  #define PCIE_ATU_UPPER_TARGET		0x91C
>>>
>>> +#define PCIE_MISC_CONTROL_1_OFF		0x8BC
>>> +#define PCIE_DBI_RO_WR_EN		(0x1 << 0)
>>
>> Does those registers exist for dwc version 4.01a?
> 
> Joao, can you help to check this?
> I referred to DesignWare cores PCI Express controller databook version 4.21a.
> The Freescale Layerscape implement does not export the version of designware PCIe controller, I don't know which versions have those registers, if it does not work on qcom platform, I will remove the qcom related changes.

I can query the R&D, but I think it won't be very useful since the qcom' SoC do
not implement the registers (if they actually exist). I think the best way is
not to use this in qcom' SoC (maybe others should make sure their SoCs contain
these registers).

Thanks,
Joao

> 
>>
>> I managed to test 6/9, 8/9 and 9/9 on qcom platform (apq8064) which has
>> 4.01a version and it doesn't work, i.e. the PCI_CLASS_BRIDGE_PCI is not
>> returned when read PCI_CLASS_DEVICE offset.
>>
>>> +
>>>  /*
>>>   * iATU Unroll-specific register definitions
>>>   * From 4.80 core version the address translation will be made by
>>> unroll @@ -279,6 +282,28 @@ static inline u32 dw_pcie_readl_dbi2(struct
>> dw_pcie *pci, u32 reg)
>>>  	return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4);  }
>>>
>>> +static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci) {
>>> +	u32 reg;
>>> +	u32 val;
>>> +
>>> +	reg = PCIE_MISC_CONTROL_1_OFF;
>>> +	val = dw_pcie_readl_dbi(pci, reg);
>>> +	val |= PCIE_DBI_RO_WR_EN;
>>> +	dw_pcie_writel_dbi(pci, reg, val);
>>> +}
>>> +
>>> +static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci) {
>>> +	u32 reg;
>>> +	u32 val;
>>> +
>>> +	reg = PCIE_MISC_CONTROL_1_OFF;
>>> +	val = dw_pcie_readl_dbi(pci, reg);
>>> +	val &= ~PCIE_DBI_RO_WR_EN;
>>> +	dw_pcie_writel_dbi(pci, reg, val);
>>> +}
>>> +
>>>  #ifdef CONFIG_PCIE_DW_HOST
>>>  irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);  void
>>> dw_pcie_msi_init(struct pcie_port *pp);
>>>
> 
> Thanks,
> Zhiqiang
> 

RE: [PATCHv3 6/9] PCI: designware: add accessors for write permission of DBI read-only registers

[Z.q. Hou]

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[PATCHv3 7/9] PCI: layerscape: use accessors to enable/disable DBI RO registers' write permission

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Use the accessors instead accessing the DBI read-only write enable
register directly.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
 - No change

 drivers/pci/dwc/pci-layerscape.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 44a603d..0c1330f 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -33,7 +33,6 @@
 
 /* PEX Internal Configuration Registers */
 #define PCIE_STRFMR1		0x71c /* Symbol Timer & Filter Mask Register1 */
-#define PCIE_DBI_RO_WR_EN	0x8bc /* DBI Read-Only Write Enable Register */
 
 #define PCIE_IATU_NUM		6
 
@@ -145,10 +144,10 @@ static int ls_pcie_host_init(struct pcie_port *pp)
 	 */
 	ls_pcie_disable_outbound_atus(pcie);
 
-	iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
+	dw_pcie_dbi_ro_wr_en(pci);
 	ls_pcie_fix_class(pcie);
 	ls_pcie_clear_multifunction(pcie);
-	iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
+	dw_pcie_dbi_ro_wr_dis(pci);
 
 	ls_pcie_drop_msg_tlp(pcie);
 
-- 
2.1.0.27.g96db324

[PATCHv3 8/9] PCI: designware: enable write permission before updating DBI RO registers

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The existing fix doesn't actually work because the Class register and
interrupt PIN register are read-only, so it must enable the write
permission before writing the correct value to these registers.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
 - Add the same fixup for interrupt pin code.

 drivers/pci/dwc/pcie-designware-host.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index 1576211..582f5cc 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -597,10 +597,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
 
 	/* setup interrupt pins */
+	dw_pcie_dbi_ro_wr_en(pci);
 	val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
 	val &= 0xffff00ff;
 	val |= 0x00000100;
 	dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
+	dw_pcie_dbi_ro_wr_dis(pci);
 
 	/* setup bus numbers */
 	val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
@@ -637,8 +639,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 
 	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
 
+	/* Enable write permission for the DBI read-only register */
+	dw_pcie_dbi_ro_wr_en(pci);
 	/* program correct class for RC */
 	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
+	/* Better disable write permission right after the update */
+	dw_pcie_dbi_ro_wr_dis(pci);
 
 	dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
 	val |= PORT_LOGIC_SPEED_CHANGE;
-- 
2.1.0.27.g96db324

[PATCHv3 9/9] PCI: dwc: remove the obsolete fixups

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Now, the dw_pcie_setup_rc() works well, so remove the obsolete fixups:
Remove the Class field fix code from layerscape pcie driver.
Remove the implement of .rd_own_conf() from qcom pcie driver, which
is aim to correct the Class code value read from the config space.
Remove the line to enable write permission of DBI RO register from
artpec6 pcie driver.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V3:
 - Add the removing of the obsolete fixups from qcom and artpec6 pcie driver

 drivers/pci/dwc/pci-layerscape.c |  9 ---------
 drivers/pci/dwc/pcie-artpec6.c   |  6 ------
 drivers/pci/dwc/pcie-qcom.c      | 17 -----------------
 3 files changed, 32 deletions(-)

diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 0c1330f..d22ed57 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -73,14 +73,6 @@ static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
 	iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE);
 }
 
-/* Fix class value */
-static void ls_pcie_fix_class(struct ls_pcie *pcie)
-{
-	struct dw_pcie *pci = pcie->pci;
-
-	iowrite16(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE);
-}
-
 /* Drop MSG TLP except for Vendor MSG */
 static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
 {
@@ -145,7 +137,6 @@ static int ls_pcie_host_init(struct pcie_port *pp)
 	ls_pcie_disable_outbound_atus(pcie);
 
 	dw_pcie_dbi_ro_wr_en(pci);
-	ls_pcie_fix_class(pcie);
 	ls_pcie_clear_multifunction(pcie);
 	dw_pcie_dbi_ro_wr_dis(pci);
 
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index 5d81f1d..d153491 100644
--- a/drivers/pci/dwc/pcie-artpec6.c
+++ b/drivers/pci/dwc/pcie-artpec6.c
@@ -141,12 +141,6 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
 	artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
 	usleep_range(100, 200);
 
-	/*
-	 * Enable writing to config regs. This is required as the Synopsys
-	 * driver changes the class code. That register needs DBI write enable.
-	 */
-	dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
-
 	/* setup root complex */
 	dw_pcie_setup_rc(pp);
 
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
index 871e7d9..4fb3ce0d 100644
--- a/drivers/pci/dwc/pcie-qcom.c
+++ b/drivers/pci/dwc/pcie-qcom.c
@@ -948,25 +948,8 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
 	return ret;
 }
 
-static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
-				 u32 *val)
-{
-	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
-
-	/* the device class is not reported correctly from the register */
-	if (where == PCI_CLASS_REVISION && size == 4) {
-		*val = readl(pci->dbi_base + PCI_CLASS_REVISION);
-		*val &= 0xff;	/* keep revision id */
-		*val |= PCI_CLASS_BRIDGE_PCI << 16;
-		return PCIBIOS_SUCCESSFUL;
-	}
-
-	return dw_pcie_read(pci->dbi_base + where, size, val);
-}
-
 static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
 	.host_init = qcom_pcie_host_init,
-	.rd_own_conf = qcom_pcie_rd_own_conf,
 };
 
 static const struct qcom_pcie_ops ops_v0 = {
-- 
2.1.0.27.g96db324