From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mout.kundenserver.de ([212.227.126.187]:57105 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751470AbaLQWRW (ORCPT ); Wed, 17 Dec 2014 17:17:22 -0500 From: Arnd Bergmann To: Gabriel FERNANDEZ Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Srinivas Kandagatla , Maxime Coquelin , Patrice Chotard , Russell King , Bjorn Helgaas , Mohit Kumar , Jingoo Han , Grant Likely , Gabriel Fernandez , Fabrice Gasnier , Viresh Kumar , Thierry Reding , Minghuan Lian , Magnus Damm , Will Deacon , Tanmay Inamdar , Murali Karicheri , Kishon Vijay Abraham I , Pratyush Anand , Sachin Kamat , Andrew Lunn , Liviu Dudau , Srikanth Thokala , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@stlinux.com, linux-pci@vger.kernel.org, Lee Jones Subject: Re: [PATCH 4/5] PCI: designware: Add setup bus-related to pcie_host_ops Date: Wed, 17 Dec 2014 23:16:12 +0100 Message-ID: <1507589.aeTeyNn1QF@wuerfel> In-Reply-To: <1418812486-12394-5-git-send-email-gabriel.fernandez@linaro.org> References: <1418812486-12394-1-git-send-email-gabriel.fernandez@linaro.org> <1418812486-12394-5-git-send-email-gabriel.fernandez@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Sender: linux-pci-owner@vger.kernel.org List-ID: On Wednesday 17 December 2014 11:34:45 Gabriel FERNANDEZ wrote: > ST sti SoCs PCIe IPs are built around DesignWare IP Core. > But in these SoCs PCIe IP doesn't support IO. > > To support this, add setup_bus() to pcie_host_ops. > > Signed-off-by: Fabrice Gasnier > Signed-off-by: Gabriel Fernandez The dw-pcie driver should be able to tell whether the device has an I/O space or not, and do the right thing based on that. Don't add an implementation specific callback for that. Arnd