[PATCH V2 0/7] Tegra PCIe end point config space map code refactoring

[PATCH V2 0/7] Tegra PCIe end point config space map code refactoring

[Vidya Sagar]

PCIe host controller in Tegra SoCs has 1GB of aperture available
for mapping end points config space, IO and BARs. In that, currently
256MB is being reserved for mapping end points configuration space
which leaves less memory space available for mapping end points BARs
on some of the platforms.
This patch series attempts to use only 4K space from 1GB aperture to
access end points configuration space.

Currently, this change benefits T20 and T186 in saving (i.e. repurposed
to use for BAR mapping) physical space as well as kernel virtual mapping space,
it saves only kernel virtual address space in T30, T124, T132 and T210.

NOTE: Both driver and DT changes are inter-dependent and hence need to go together

Testing Done on T124, T210 & T186:
 Enumeration and basic functionality of immediate devices
 Enumeration of devices behind a PCIe switch
 Complete 4K configuration space access

Vidya Sagar (7):
  PCI: tegra: refactor config space mapping code
  ARM: tegra: limit PCIe config space mapping to 4K for T20
  ARM: tegra: limit PCIe config space mapping to 4K for T30
  ARM: tegra: limit PCIe config space mapping to 4K for T124
  ARM64: tegra: limit PCIe config space mapping to 4K for T132
  ARM64: tegra: limit PCIe config space mapping to 4K for T210
  ARM64: tegra: limit PCIe config space mapping to 4K for T186

 arch/arm/boot/dts/tegra124.dtsi          |   2 +-
 arch/arm/boot/dts/tegra20.dtsi           |   8 +--
 arch/arm/boot/dts/tegra30.dtsi           |   2 +-
 arch/arm64/boot/dts/nvidia/tegra132.dtsi |   2 +-
 arch/arm64/boot/dts/nvidia/tegra186.dtsi |   8 +--
 arch/arm64/boot/dts/nvidia/tegra210.dtsi |   2 +-
 drivers/pci/host/pci-tegra.c             | 109 +++++++++----------------------
 7 files changed, 42 insertions(+), 91 deletions(-)

-- 
2.7.4

[PATCH V2 1/7] PCI: tegra: refactor config space mapping code

[Vidya Sagar]

use only 4K space from available 1GB PCIe aperture to access
end points configuration space by dynamically moving AFI_AXI_BAR
base address and always making sure that the desired location
to be accessed for generating required config space access falls
in the 4K space reserved for this purpose. This would give more
space for mapping end point device's BARs on some of Tegra platforms

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V2:
* restored tegra_pcie_conf_offset() after extending it to include bus number
* removed tegra_pcie_bus_alloc() and merged some of its contents with tegra_pcie_add_bus()
* replaced ioremap() with devm_ioremap()

 drivers/pci/host/pci-tegra.c | 109 ++++++++++++-------------------------------
 1 file changed, 30 insertions(+), 79 deletions(-)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index af8b05614f87..d080adeb8540 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -274,6 +274,8 @@ struct tegra_pcie {
 	struct list_head buses;
 	struct resource *cs;
 
+	void __iomem *cfg_va_base;
+
 	struct resource io;
 	struct resource pio;
 	struct resource mem;
@@ -322,7 +324,6 @@ struct tegra_pcie_port {
 };
 
 struct tegra_pcie_bus {
-	struct vm_struct *area;
 	struct list_head list;
 	unsigned int nr;
 };
@@ -362,69 +363,17 @@ static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
  *
  * Mapping the whole extended configuration space would require 256 MiB of
  * virtual address space, only a small part of which will actually be used.
- * To work around this, a 1 MiB of virtual addresses are allocated per bus
- * when the bus is first accessed. When the physical range is mapped, the
- * the bus number bits are hidden so that the extended register number bits
- * appear as bits [19:16]. Therefore the virtual mapping looks like this:
- *
- *    [19:16] extended register number
- *    [15:11] device number
- *    [10: 8] function number
- *    [ 7: 0] register number
- *
- * This is achieved by stitching together 16 chunks of 64 KiB of physical
- * address space via the MMU.
+ * To work around this, a 4K of region is used to generate required
+ * configuration transaction with relevant B:D:F values. This is achieved by
+ * dynamically programming base address and size of AFI_AXI_BAR used for
+ * end point config space mapping to make sure that the address (access to
+ * which generates correct config transaction) falls in this 4K region
  */
-static unsigned long tegra_pcie_conf_offset(unsigned int devfn, int where)
-{
-	return ((where & 0xf00) << 8) | (PCI_SLOT(devfn) << 11) |
-	       (PCI_FUNC(devfn) << 8) | (where & 0xfc);
-}
-
-static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie,
-						   unsigned int busnr)
+static unsigned long tegra_pcie_conf_offset(unsigned char b, unsigned int devfn,
+					    int where)
 {
-	struct device *dev = pcie->dev;
-	pgprot_t prot = pgprot_noncached(PAGE_KERNEL);
-	phys_addr_t cs = pcie->cs->start;
-	struct tegra_pcie_bus *bus;
-	unsigned int i;
-	int err;
-
-	bus = kzalloc(sizeof(*bus), GFP_KERNEL);
-	if (!bus)
-		return ERR_PTR(-ENOMEM);
-
-	INIT_LIST_HEAD(&bus->list);
-	bus->nr = busnr;
-
-	/* allocate 1 MiB of virtual addresses */
-	bus->area = get_vm_area(SZ_1M, VM_IOREMAP);
-	if (!bus->area) {
-		err = -ENOMEM;
-		goto free;
-	}
-
-	/* map each of the 16 chunks of 64 KiB each */
-	for (i = 0; i < 16; i++) {
-		unsigned long virt = (unsigned long)bus->area->addr +
-				     i * SZ_64K;
-		phys_addr_t phys = cs + i * SZ_16M + busnr * SZ_64K;
-
-		err = ioremap_page_range(virt, virt + SZ_64K, phys, prot);
-		if (err < 0) {
-			dev_err(dev, "ioremap_page_range() failed: %d\n", err);
-			goto unmap;
-		}
-	}
-
-	return bus;
-
-unmap:
-	vunmap(bus->area->addr);
-free:
-	kfree(bus);
-	return ERR_PTR(err);
+	return (b << 16) | (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) |
+	       (((where & 0xf00) >> 8) << 24) | (where & 0xff);
 }
 
 static int tegra_pcie_add_bus(struct pci_bus *bus)
@@ -433,10 +382,13 @@ static int tegra_pcie_add_bus(struct pci_bus *bus)
 	struct tegra_pcie *pcie = pci_host_bridge_priv(host);
 	struct tegra_pcie_bus *b;
 
-	b = tegra_pcie_bus_alloc(pcie, bus->number);
-	if (IS_ERR(b))
+	b = kzalloc(sizeof(*b), GFP_KERNEL);
+	if (!b)
 		return PTR_ERR(b);
 
+	INIT_LIST_HEAD(&b->list);
+	b->nr = bus->number;
+
 	list_add_tail(&b->list, &pcie->buses);
 
 	return 0;
@@ -450,7 +402,6 @@ static void tegra_pcie_remove_bus(struct pci_bus *child)
 
 	list_for_each_entry_safe(bus, tmp, &pcie->buses, list) {
 		if (bus->nr == child->number) {
-			vunmap(bus->area->addr);
 			list_del(&bus->list);
 			kfree(bus);
 			break;
@@ -464,8 +415,9 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus,
 {
 	struct pci_host_bridge *host = pci_find_host_bridge(bus);
 	struct tegra_pcie *pcie = pci_host_bridge_priv(host);
-	struct device *dev = pcie->dev;
 	void __iomem *addr = NULL;
+	u32 val = 0;
+	u32 offset = 0;
 
 	if (bus->number == 0) {
 		unsigned int slot = PCI_SLOT(devfn);
@@ -478,19 +430,11 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus,
 			}
 		}
 	} else {
-		struct tegra_pcie_bus *b;
-
-		list_for_each_entry(b, &pcie->buses, list)
-			if (b->nr == bus->number)
-				addr = (void __iomem *)b->area->addr;
-
-		if (!addr) {
-			dev_err(dev, "failed to map cfg. space for bus %u\n",
-				bus->number);
-			return NULL;
-		}
-
-		addr += tegra_pcie_conf_offset(devfn, where);
+		offset = tegra_pcie_conf_offset(bus->number, devfn, where);
+		addr = pcie->cfg_va_base + (offset & (SZ_4K - 1));
+		val = offset & ~(SZ_4K - 1);
+		afi_writel(pcie, pcie->cs->start - val, AFI_AXI_BAR0_START);
+		afi_writel(pcie, (val + SZ_4K) >> 12, AFI_AXI_BAR0_SZ);
 	}
 
 	return addr;
@@ -1340,6 +1284,13 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
 		goto poweroff;
 	}
 
+	pcie->cfg_va_base = devm_ioremap(dev, pcie->cs->start, SZ_4K);
+	if (!pcie->cfg_va_base) {
+		dev_err(pcie->dev, "failed to ioremap config space\n");
+		err = -EADDRNOTAVAIL;
+		goto poweroff;
+	}
+
 	/* request interrupt */
 	err = platform_get_irq_byname(pdev, "intr");
 	if (err < 0) {
-- 
2.7.4

[PATCH V2 2/7] ARM: tegra: limit PCIe config space mapping to 4K for T20

[Vidya Sagar]

reduces PCIe end point config space mapping size from its
current 256MB to 4K to give more space for BAR mapping

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V2:
* no changes in this patch

 arch/arm/boot/dts/tegra20.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 7c85f97f72ea..4c761a60cdf7 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -591,7 +591,7 @@
 		device_type = "pci";
 		reg = <0x80003000 0x00000800   /* PADS registers */
 		       0x80003800 0x00000200   /* AFI registers */
-		       0x90000000 0x10000000>; /* configuration space */
+		       0x82000000 0x00001000>; /* configuration space */
 		reg-names = "pads", "afi", "cs";
 		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
 			      GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
@@ -607,9 +607,9 @@
 
 		ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000   /* port 0 registers */
 			  0x82000000 0 0x80001000 0x80001000 0 0x00001000   /* port 1 registers */
-			  0x81000000 0 0          0x82000000 0 0x00010000   /* downstream I/O */
-			  0x82000000 0 0xa0000000 0xa0000000 0 0x08000000   /* non-prefetchable memory */
-			  0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
+			  0x81000000 0 0          0x82001000 0 0x00010000   /* downstream I/O */
+			  0x82000000 0 0x82100000 0x82100000 0 0x05F00000   /* non-prefetchable memory */
+			  0xc2000000 0 0x88000000 0x88000000 0 0x38000000>; /* prefetchable memory */
 
 		clocks = <&tegra_car TEGRA20_CLK_PEX>,
 			 <&tegra_car TEGRA20_CLK_AFI>,
-- 
2.7.4

[PATCH V2 3/7] ARM: tegra: limit PCIe config space mapping to 4K for T30

[Vidya Sagar]

reduces PCIe config space mapping size from its current
256MB to 4K to have only 4K of virtual memory mapping and to be
in line with driver implementation

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V2:
* no changes in this patch

 arch/arm/boot/dts/tegra30.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 13960fda7471..b23171f2b86f 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -15,7 +15,7 @@
 		device_type = "pci";
 		reg = <0x00003000 0x00000800   /* PADS registers */
 		       0x00003800 0x00000200   /* AFI registers */
-		       0x10000000 0x10000000>; /* configuration space */
+		       0x1FFFF000 0x00001000>; /* configuration space */
 		reg-names = "pads", "afi", "cs";
 		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
 			      GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
-- 
2.7.4

[PATCH V2 4/7] ARM: tegra: limit PCIe config space mapping to 4K for T124

[Vidya Sagar]

reduces PCIe config space mapping size from its current 256MB
to 4K to have only 4K of virtual memory mapping and to be
in line with driver implementation

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V2:
* no changes in this patch

 arch/arm/boot/dts/tegra124.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 8baf00b89efb..e3cd9dca57cb 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -19,7 +19,7 @@
 		device_type = "pci";
 		reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
 		       0x0 0x01003800 0x0 0x00000800   /* AFI registers */
-		       0x0 0x02000000 0x0 0x10000000>; /* configuration space */
+		       0x0 0x11FFF000 0x0 0x00001000>; /* configuration space */
 		reg-names = "pads", "afi", "cs";
 		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
 			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
-- 
2.7.4

[PATCH V2 5/7] ARM64: tegra: limit PCIe config space mapping to 4K for T132

[Vidya Sagar]

reduces PCIe config space mapping size from its current 256MB
to 4K to have only 4K of virtual memory mapping and to be
in line with driver implementation

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V2:
* no changes in this patch

 arch/arm64/boot/dts/nvidia/tegra132.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
index c2f0f2743578..2f0ff087112e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
@@ -17,7 +17,7 @@
 		device_type = "pci";
 		reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
 		       0x0 0x01003800 0x0 0x00000800   /* AFI registers */
-		       0x0 0x02000000 0x0 0x10000000>; /* configuration space */
+		       0x0 0x11FFF000 0x0 0x00001000>; /* configuration space */
 		reg-names = "pads", "afi", "cs";
 		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
 			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
-- 
2.7.4

[PATCH V2 6/7] ARM64: tegra: limit PCIe config space mapping to 4K for T210

[Vidya Sagar]

reduces PCIe config space mapping size from its current 256MB
to 4K to have only 4K of virtual memory mapping and to be
in line with driver implementation

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V2:
* no changes in this patch

 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 29f471e0f22a..8cad2516597b 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -16,7 +16,7 @@
 		device_type = "pci";
 		reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
 		       0x0 0x01003800 0x0 0x00000800   /* AFI registers */
-		       0x0 0x02000000 0x0 0x10000000>; /* configuration space */
+		       0x0 0x11FFF000 0x0 0x00001000>; /* configuration space */
 		reg-names = "pads", "afi", "cs";
 		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
 			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
-- 
2.7.4

[PATCH V2 7/7] ARM64: tegra: limit PCIe config space mapping to 4K for T186

[Vidya Sagar]

reduces PCIe config space mapping size from its current 256MB
to 4K to have only 4K of virtual memory mapping and to be
in line with driver implementation

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 7c3a2bdd4644..c64550c32d72 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -361,7 +361,7 @@
 		device_type = "pci";
 		reg = <0x0 0x10003000 0x0 0x00000800   /* PADS registers */
 		       0x0 0x10003800 0x0 0x00000800   /* AFI registers */
-		       0x0 0x40000000 0x0 0x10000000>; /* configuration space */
+		       0x0 0x40000000 0x0 0x00001000>; /* configuration space */
 		reg-names = "pads", "afi", "cs";
 
 		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
@@ -379,9 +379,9 @@
 		ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000   /* port 0 configuration space */
 			  0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000   /* port 1 configuration space */
 			  0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000   /* port 2 configuration space */
-			  0x81000000 0 0x0        0x0 0x50000000 0 0x00010000   /* downstream I/O (64 KiB) */
-			  0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000   /* non-prefetchable memory (127 MiB) */
-			  0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
+			  0x81000000 0 0x0        0x0 0x40001000 0 0x00010000   /* downstream I/O (64 KiB) */
+			  0x82000000 0 0x40100000 0x0 0x40100000 0 0x07F00000   /* non-prefetchable memory (127 MiB) */
+			  0xc2000000 0 0x48000000 0x0 0x48000000 0 0x38000000>; /* prefetchable memory (896 MiB) */
 
 		clocks = <&bpmp TEGRA186_CLK_AFI>,
 			 <&bpmp TEGRA186_CLK_PCIE>,
-- 
2.7.4

Re: [PATCH V2 0/7] Tegra PCIe end point config space map code refactoring

[Rob Herring]

On Mon, Oct 23, 2017 at 9:35 AM, Vidya Sagar <vidyas@nvidia.com> wrote:
> PCIe host controller in Tegra SoCs has 1GB of aperture available
> for mapping end points config space, IO and BARs. In that, currently
> 256MB is being reserved for mapping end points configuration space
> which leaves less memory space available for mapping end points BARs
> on some of the platforms.
> This patch series attempts to use only 4K space from 1GB aperture to
> access end points configuration space.
>
> Currently, this change benefits T20 and T186 in saving (i.e. repurposed
> to use for BAR mapping) physical space as well as kernel virtual mapping space,
> it saves only kernel virtual address space in T30, T124, T132 and T210.
>
> NOTE: Both driver and DT changes are inter-dependent and hence need to go together

You are breaking compatibility with any other OS.

Can't this easily be solved within the kernel by adjusting the
resource size? To save the virtual space, you only need patch 1 and
don't need the DT change. The DT change is just for phys address space
for BARs.

>
> Testing Done on T124, T210 & T186:
>  Enumeration and basic functionality of immediate devices
>  Enumeration of devices behind a PCIe switch
>  Complete 4K configuration space access
>
> Vidya Sagar (7):
>   PCI: tegra: refactor config space mapping code
>   ARM: tegra: limit PCIe config space mapping to 4K for T20
>   ARM: tegra: limit PCIe config space mapping to 4K for T30
>   ARM: tegra: limit PCIe config space mapping to 4K for T124
>   ARM64: tegra: limit PCIe config space mapping to 4K for T132
>   ARM64: tegra: limit PCIe config space mapping to 4K for T210
>   ARM64: tegra: limit PCIe config space mapping to 4K for T186
>
>  arch/arm/boot/dts/tegra124.dtsi          |   2 +-
>  arch/arm/boot/dts/tegra20.dtsi           |   8 +--
>  arch/arm/boot/dts/tegra30.dtsi           |   2 +-
>  arch/arm64/boot/dts/nvidia/tegra132.dtsi |   2 +-
>  arch/arm64/boot/dts/nvidia/tegra186.dtsi |   8 +--
>  arch/arm64/boot/dts/nvidia/tegra210.dtsi |   2 +-
>  drivers/pci/host/pci-tegra.c             | 109 +++++++++----------------------
>  7 files changed, 42 insertions(+), 91 deletions(-)
>
> --
> 2.7.4
>

Re: [PATCH V2 0/7] Tegra PCIe end point config space map code refactoring

[Vidya Sagar]

On Monday 23 October 2017 08:40 PM, Rob Herring wrote:
> On Mon, Oct 23, 2017 at 9:35 AM, Vidya Sagar <vidyas@nvidia.com> wrote:
>> PCIe host controller in Tegra SoCs has 1GB of aperture available
>> for mapping end points config space, IO and BARs. In that, currently
>> 256MB is being reserved for mapping end points configuration space
>> which leaves less memory space available for mapping end points BARs
>> on some of the platforms.
>> This patch series attempts to use only 4K space from 1GB aperture to
>> access end points configuration space.
>>
>> Currently, this change benefits T20 and T186 in saving (i.e. repurposed
>> to use for BAR mapping) physical space as well as kernel virtual mapping space,
>> it saves only kernel virtual address space in T30, T124, T132 and T210.
>>
>> NOTE: Both driver and DT changes are inter-dependent and hence need to go together
> You are breaking compatibility with any other OS.
>
> Can't this easily be solved within the kernel by adjusting the
> resource size? To save the virtual space, you only need patch 1 and
> don't need the DT change. The DT change is just for phys address space
> for BARs.
In case of T20 & T186, DT change is required to re-purpose address space 
which otherwise
is used for config space mapping to map BARs. In case of other chips, DT 
changes
are also required because the 4K being used for mapping config space is 
taken from the
last 4K chunk of 256MB instead of first 4K chunk to align with driver 
change.
>> Testing Done on T124, T210 & T186:
>>   Enumeration and basic functionality of immediate devices
>>   Enumeration of devices behind a PCIe switch
>>   Complete 4K configuration space access
>>
>> Vidya Sagar (7):
>>    PCI: tegra: refactor config space mapping code
>>    ARM: tegra: limit PCIe config space mapping to 4K for T20
>>    ARM: tegra: limit PCIe config space mapping to 4K for T30
>>    ARM: tegra: limit PCIe config space mapping to 4K for T124
>>    ARM64: tegra: limit PCIe config space mapping to 4K for T132
>>    ARM64: tegra: limit PCIe config space mapping to 4K for T210
>>    ARM64: tegra: limit PCIe config space mapping to 4K for T186
>>
>>   arch/arm/boot/dts/tegra124.dtsi          |   2 +-
>>   arch/arm/boot/dts/tegra20.dtsi           |   8 +--
>>   arch/arm/boot/dts/tegra30.dtsi           |   2 +-
>>   arch/arm64/boot/dts/nvidia/tegra132.dtsi |   2 +-
>>   arch/arm64/boot/dts/nvidia/tegra186.dtsi |   8 +--
>>   arch/arm64/boot/dts/nvidia/tegra210.dtsi |   2 +-
>>   drivers/pci/host/pci-tegra.c             | 109 +++++++++----------------------
>>   7 files changed, 42 insertions(+), 91 deletions(-)
>>
>> --
>> 2.7.4
>>

Re: [PATCH V2 0/7] Tegra PCIe end point config space map code refactoring

[Mikko Perttunen]

On 10/23/2017 06:24 PM, Vidya Sagar wrote:
> 
> 
> On Monday 23 October 2017 08:40 PM, Rob Herring wrote:
>> On Mon, Oct 23, 2017 at 9:35 AM, Vidya Sagar <vidyas@nvidia.com> wrote:
>>> PCIe host controller in Tegra SoCs has 1GB of aperture available
>>> for mapping end points config space, IO and BARs. In that, currently
>>> 256MB is being reserved for mapping end points configuration space
>>> which leaves less memory space available for mapping end points BARs
>>> on some of the platforms.
>>> This patch series attempts to use only 4K space from 1GB aperture to
>>> access end points configuration space.
>>>
>>> Currently, this change benefits T20 and T186 in saving (i.e. repurposed
>>> to use for BAR mapping) physical space as well as kernel virtual 
>>> mapping space,
>>> it saves only kernel virtual address space in T30, T124, T132 and T210.
>>>
>>> NOTE: Both driver and DT changes are inter-dependent and hence need 
>>> to go together
>> You are breaking compatibility with any other OS.
>>
>> Can't this easily be solved within the kernel by adjusting the
>> resource size? To save the virtual space, you only need patch 1 and
>> don't need the DT change. The DT change is just for phys address space
>> for BARs.
> In case of T20 & T186, DT change is required to re-purpose address space 
> which otherwise
> is used for config space mapping to map BARs. In case of other chips, DT 
> changes
> are also required because the 4K being used for mapping config space is 
> taken from the
> last 4K chunk of 256MB instead of first 4K chunk to align with driver 
> change.

The kernel must continue to work with older device trees. This is a 
pretty hard rule.

Mikko

>>> Testing Done on T124, T210 & T186:
>>>   Enumeration and basic functionality of immediate devices
>>>   Enumeration of devices behind a PCIe switch
>>>   Complete 4K configuration space access
>>>
>>> Vidya Sagar (7):
>>>    PCI: tegra: refactor config space mapping code
>>>    ARM: tegra: limit PCIe config space mapping to 4K for T20
>>>    ARM: tegra: limit PCIe config space mapping to 4K for T30
>>>    ARM: tegra: limit PCIe config space mapping to 4K for T124
>>>    ARM64: tegra: limit PCIe config space mapping to 4K for T132
>>>    ARM64: tegra: limit PCIe config space mapping to 4K for T210
>>>    ARM64: tegra: limit PCIe config space mapping to 4K for T186
>>>
>>>   arch/arm/boot/dts/tegra124.dtsi          |   2 +-
>>>   arch/arm/boot/dts/tegra20.dtsi           |   8 +--
>>>   arch/arm/boot/dts/tegra30.dtsi           |   2 +-
>>>   arch/arm64/boot/dts/nvidia/tegra132.dtsi |   2 +-
>>>   arch/arm64/boot/dts/nvidia/tegra186.dtsi |   8 +--
>>>   arch/arm64/boot/dts/nvidia/tegra210.dtsi |   2 +-
>>>   drivers/pci/host/pci-tegra.c             | 109 
>>> +++++++++----------------------
>>>   7 files changed, 42 insertions(+), 91 deletions(-)
>>>
>>> -- 
>>> 2.7.4
>>>
> 
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Re: [PATCH V2 0/7] Tegra PCIe end point config space map code refactoring

[Vidya Sagar]

On Monday 23 October 2017 09:46 PM, Mikko Perttunen wrote:
> On 10/23/2017 06:24 PM, Vidya Sagar wrote:
>>
>>
>> On Monday 23 October 2017 08:40 PM, Rob Herring wrote:
>>> On Mon, Oct 23, 2017 at 9:35 AM, Vidya Sagar <vidyas@nvidia.com> wrote:
>>>> PCIe host controller in Tegra SoCs has 1GB of aperture available
>>>> for mapping end points config space, IO and BARs. In that, currently
>>>> 256MB is being reserved for mapping end points configuration space
>>>> which leaves less memory space available for mapping end points BARs
>>>> on some of the platforms.
>>>> This patch series attempts to use only 4K space from 1GB aperture to
>>>> access end points configuration space.
>>>>
>>>> Currently, this change benefits T20 and T186 in saving (i.e. 
>>>> repurposed
>>>> to use for BAR mapping) physical space as well as kernel virtual 
>>>> mapping space,
>>>> it saves only kernel virtual address space in T30, T124, T132 and 
>>>> T210.
>>>>
>>>> NOTE: Both driver and DT changes are inter-dependent and hence need 
>>>> to go together
>>> You are breaking compatibility with any other OS.
>>>
>>> Can't this easily be solved within the kernel by adjusting the
>>> resource size? To save the virtual space, you only need patch 1 and
>>> don't need the DT change. The DT change is just for phys address space
>>> for BARs.
>> In case of T20 & T186, DT change is required to re-purpose address 
>> space which otherwise
>> is used for config space mapping to map BARs. In case of other chips, 
>> DT changes
>> are also required because the 4K being used for mapping config space 
>> is taken from the
>> last 4K chunk of 256MB instead of first 4K chunk to align with driver 
>> change.
>
> The kernel must continue to work with older device trees. This is a 
> pretty hard rule.
I think I can come up with a change only in driver to take care of this, 
although, to start with, I may not
be able to give more space for BAR mapping, but we can have a DT-only 
change later on for that.
>
> Mikko
>
>>>> Testing Done on T124, T210 & T186:
>>>>   Enumeration and basic functionality of immediate devices
>>>>   Enumeration of devices behind a PCIe switch
>>>>   Complete 4K configuration space access
>>>>
>>>> Vidya Sagar (7):
>>>>    PCI: tegra: refactor config space mapping code
>>>>    ARM: tegra: limit PCIe config space mapping to 4K for T20
>>>>    ARM: tegra: limit PCIe config space mapping to 4K for T30
>>>>    ARM: tegra: limit PCIe config space mapping to 4K for T124
>>>>    ARM64: tegra: limit PCIe config space mapping to 4K for T132
>>>>    ARM64: tegra: limit PCIe config space mapping to 4K for T210
>>>>    ARM64: tegra: limit PCIe config space mapping to 4K for T186
>>>>
>>>>   arch/arm/boot/dts/tegra124.dtsi          |   2 +-
>>>>   arch/arm/boot/dts/tegra20.dtsi           |   8 +--
>>>>   arch/arm/boot/dts/tegra30.dtsi           |   2 +-
>>>>   arch/arm64/boot/dts/nvidia/tegra132.dtsi |   2 +-
>>>>   arch/arm64/boot/dts/nvidia/tegra186.dtsi |   8 +--
>>>>   arch/arm64/boot/dts/nvidia/tegra210.dtsi |   2 +-
>>>>   drivers/pci/host/pci-tegra.c             | 109 
>>>> +++++++++----------------------
>>>>   7 files changed, 42 insertions(+), 91 deletions(-)
>>>>
>>>> -- 
>>>> 2.7.4
>>>>
>>
>> -- 
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