From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: <thierry.reding@gmail.com>, <bhelgaas@google.com>,
<jonathanh@nvidia.com>
Cc: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<vidyas@nvidia.com>, <kthota@nvidia.com>,
Manikanta Maddireddy <mmaddireddy@nvidia.com>
Subject: [PATCH 12/12] PCI: tegra: Update flow control threshold in Tegra210
Date: Sat, 28 Oct 2017 00:59:29 +0530 [thread overview]
Message-ID: <1509132569-9398-13-git-send-email-mmaddireddy@nvidia.com> (raw)
In-Reply-To: <1509132569-9398-1-git-send-email-mmaddireddy@nvidia.com>
Recommended update FC threshold in Tegra210 is 0x60 for best performance
of x1 link. Setting this to 0x60 provides the best balance between number
of UpdateFC and read data sent over the link.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
drivers/pci/host/pci-tegra.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index db1ce74ba64a..da5f4998f149 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -221,6 +221,7 @@
#define RP_VEND_XP_OPPORTUNISTIC_ACK (1 << 27)
#define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28)
#define RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK (0xff << 18)
+#define RP_VEND_XP_UPDATE_FC_THRESHOLD_T210 (0x60 << 18)
#define RP_VEND_CTL0 0xf44
#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK (0xf << 12)
@@ -321,6 +322,7 @@ struct tegra_pcie_soc {
bool update_clamp_threshold;
bool RAW_violation_fixup;
bool program_deskew_time;
+ bool updateFC_threshold;
};
static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
@@ -2229,6 +2231,13 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
value |= RP_VEND_CTL0_DSK_RST_PULSE_WIDTH;
writel(value, port->base + RP_VEND_CTL0);
}
+
+ if (soc->updateFC_threshold) {
+ value = readl(port->base + RP_VEND_XP);
+ value &= ~RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK;
+ value |= RP_VEND_XP_UPDATE_FC_THRESHOLD_T210;
+ writel(value, port->base + RP_VEND_XP);
+ }
}
/*
* FIXME: If there are no PCIe cards attached, then calling this function
@@ -2368,6 +2377,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
.update_clamp_threshold = false,
.RAW_violation_fixup = false,
.program_deskew_time = false,
+ .updateFC_threshold = false,
};
static const struct tegra_pcie_soc tegra30_pcie = {
@@ -2388,6 +2398,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
.update_clamp_threshold = false,
.RAW_violation_fixup = false,
.program_deskew_time = false,
+ .updateFC_threshold = false,
};
static const struct tegra_pcie_soc tegra124_pcie = {
@@ -2407,6 +2418,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
.update_clamp_threshold = true,
.RAW_violation_fixup = true,
.program_deskew_time = false,
+ .updateFC_threshold = false,
};
static const struct tegra_pcie_soc tegra210_pcie = {
@@ -2434,6 +2446,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
.update_clamp_threshold = true,
.RAW_violation_fixup = false,
.program_deskew_time = true,
+ .updateFC_threshold = true,
};
static const struct tegra_pcie_soc tegra186_pcie = {
@@ -2454,6 +2467,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
.update_clamp_threshold = false,
.RAW_violation_fixup = false,
.program_deskew_time = false,
+ .updateFC_threshold = false,
};
static const struct of_device_id tegra_pcie_of_match[] = {
--
2.1.4
prev parent reply other threads:[~2017-10-27 19:31 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-27 19:29 [PATCH 00/12] Enable Tegra root port features and apply SW fixups Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 01/12] PCI: tegra: Start LTSSM after programming root port Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 02/12] PCI: tegra: Move REFCLK pad settings out of phy_power_on() Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 03/12] PCI: tegra: Retrain link for Gen2 speed Manikanta Maddireddy
2017-10-29 9:34 ` Vidya Sagar
2017-10-29 9:38 ` Vidya Sagar
2017-10-30 3:51 ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 04/12] PCI: tegra: Advertise AER capability Manikanta Maddireddy
2017-10-29 9:39 ` Vidya Sagar
2017-10-30 3:54 ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 05/12] PCI: tegra: Program UPHY electrical settings in Tegra210 Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 06/12] PCI: tegra: Enable opportunistic update FC and ACK Manikanta Maddireddy
2017-10-29 9:41 ` Vidya Sagar
2017-10-30 3:55 ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 07/12] PCI: tegra: Disable AFI dynamic clock gating Manikanta Maddireddy
2017-10-29 9:42 ` Vidya Sagar
2017-10-30 3:55 ` Manikanta Maddireddy
2017-10-30 15:58 ` David Laight
2017-10-30 16:18 ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 08/12] PCI: tegra: Wait for DLLP to finish before entering L1 or L2 Manikanta Maddireddy
2017-10-29 9:42 ` Vidya Sagar
2017-10-30 3:56 ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 09/12] PCI: tegra: Enable PCIe xclk clock clamping Manikanta Maddireddy
2017-10-29 9:43 ` Vidya Sagar
2017-10-30 3:56 ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 10/12] PCI: tegra: Add SW fixup for RAW violations Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 11/12] PCI: tegra: Increase the deskew retry time Manikanta Maddireddy
2017-10-27 19:29 ` Manikanta Maddireddy [this message]
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