From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: <thierry.reding@gmail.com>, <bhelgaas@google.com>,
<jonathanh@nvidia.com>
Cc: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<vidyas@nvidia.com>, <kthota@nvidia.com>,
Manikanta Maddireddy <mmaddireddy@nvidia.com>
Subject: [PATCH 08/12] PCI: tegra: Wait for DLLP to finish before entering L1 or L2
Date: Sat, 28 Oct 2017 00:59:25 +0530 [thread overview]
Message-ID: <1509132569-9398-9-git-send-email-mmaddireddy@nvidia.com> (raw)
In-Reply-To: <1509132569-9398-1-git-send-email-mmaddireddy@nvidia.com>
Set required bit to have LTSSM wait for DLLP to finish before entering L1
or L2. This avoids truncation of PM messages which results in receiver
errors.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
drivers/pci/host/pci-tegra.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index b8cac871712b..6028d5f3d5bb 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -217,6 +217,9 @@
#define RP_VEND_CTL1 0xf48
#define RP_VEND_CTL1_ERPT (1 << 13)
+#define RP_VEND_XP_BIST 0xf4c
+#define RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE (1 << 28)
+
#define RP_VEND_CTL2 0x00000fa8
#define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
@@ -2160,6 +2163,13 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
value |= RP_VEND_XP_OPPORTUNISTIC_ACK;
value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC;
writel(value, port->base + RP_VEND_XP);
+
+ /* LTSSM will wait for DLLP to finish before entering L1 or L2,
+ * to avoid truncation of PM messages which results in receiver errors
+ */
+ value = readl(port->base + RP_VEND_XP_BIST);
+ value |= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE;
+ writel(value, port->base + RP_VEND_XP_BIST);
}
/*
* FIXME: If there are no PCIe cards attached, then calling this function
--
2.1.4
next prev parent reply other threads:[~2017-10-27 19:31 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-27 19:29 [PATCH 00/12] Enable Tegra root port features and apply SW fixups Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 01/12] PCI: tegra: Start LTSSM after programming root port Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 02/12] PCI: tegra: Move REFCLK pad settings out of phy_power_on() Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 03/12] PCI: tegra: Retrain link for Gen2 speed Manikanta Maddireddy
2017-10-29 9:34 ` Vidya Sagar
2017-10-29 9:38 ` Vidya Sagar
2017-10-30 3:51 ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 04/12] PCI: tegra: Advertise AER capability Manikanta Maddireddy
2017-10-29 9:39 ` Vidya Sagar
2017-10-30 3:54 ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 05/12] PCI: tegra: Program UPHY electrical settings in Tegra210 Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 06/12] PCI: tegra: Enable opportunistic update FC and ACK Manikanta Maddireddy
2017-10-29 9:41 ` Vidya Sagar
2017-10-30 3:55 ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 07/12] PCI: tegra: Disable AFI dynamic clock gating Manikanta Maddireddy
2017-10-29 9:42 ` Vidya Sagar
2017-10-30 3:55 ` Manikanta Maddireddy
2017-10-30 15:58 ` David Laight
2017-10-30 16:18 ` Manikanta Maddireddy
2017-10-27 19:29 ` Manikanta Maddireddy [this message]
2017-10-29 9:42 ` [PATCH 08/12] PCI: tegra: Wait for DLLP to finish before entering L1 or L2 Vidya Sagar
2017-10-30 3:56 ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 09/12] PCI: tegra: Enable PCIe xclk clock clamping Manikanta Maddireddy
2017-10-29 9:43 ` Vidya Sagar
2017-10-30 3:56 ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 10/12] PCI: tegra: Add SW fixup for RAW violations Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 11/12] PCI: tegra: Increase the deskew retry time Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 12/12] PCI: tegra: Update flow control threshold in Tegra210 Manikanta Maddireddy
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