From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from hqemgate16.nvidia.com ([216.228.121.65]:12091 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932312AbdJ0TbT (ORCPT ); Fri, 27 Oct 2017 15:31:19 -0400 From: Manikanta Maddireddy To: , , CC: , , , , Manikanta Maddireddy Subject: [PATCH 08/12] PCI: tegra: Wait for DLLP to finish before entering L1 or L2 Date: Sat, 28 Oct 2017 00:59:25 +0530 Message-ID: <1509132569-9398-9-git-send-email-mmaddireddy@nvidia.com> In-Reply-To: <1509132569-9398-1-git-send-email-mmaddireddy@nvidia.com> References: <1509132569-9398-1-git-send-email-mmaddireddy@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-pci-owner@vger.kernel.org List-ID: Set required bit to have LTSSM wait for DLLP to finish before entering L1 or L2. This avoids truncation of PM messages which results in receiver errors. Signed-off-by: Manikanta Maddireddy --- drivers/pci/host/pci-tegra.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index b8cac871712b..6028d5f3d5bb 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -217,6 +217,9 @@ #define RP_VEND_CTL1 0xf48 #define RP_VEND_CTL1_ERPT (1 << 13) +#define RP_VEND_XP_BIST 0xf4c +#define RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE (1 << 28) + #define RP_VEND_CTL2 0x00000fa8 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) @@ -2160,6 +2163,13 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) value |= RP_VEND_XP_OPPORTUNISTIC_ACK; value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC; writel(value, port->base + RP_VEND_XP); + + /* LTSSM will wait for DLLP to finish before entering L1 or L2, + * to avoid truncation of PM messages which results in receiver errors + */ + value = readl(port->base + RP_VEND_XP_BIST); + value |= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE; + writel(value, port->base + RP_VEND_XP_BIST); } /* * FIXME: If there are no PCIe cards attached, then calling this function -- 2.1.4