[PATCH 00/12] Enable Tegra root port features and apply SW fixups

[PATCH 00/12] Enable Tegra root port features and apply SW fixups

[Manikanta Maddireddy]

These series of patches does the following things,
- Deasserting pcie_xrst after programming root port to make sure that
  register programming is reflected during LTSSM
- Apply REFCLK pad settings to make sure P2P amplitude requirement is met
- Enable Gen2 link speed
- Advertise AER capability
- Program UPHY electrical settings for meeting eye diagram requirements
- Bunch of SW fixups explained in their respective commit log

Testing done on Tegra124, 210 and 186:
- PCIe link up, config read, BAR read and basic functionality of Ethernet
  card
- Link speed switch to Gen2 after link retrain
- Link speed stays in Gen1 after retrain if end point is only Gen1 capable
- Simulated AER errors and verified dmesg logs for them
- Rest of the programming is verified by dumping the registers after PCIe
link up

Manikanta Maddireddy (12):
  PCI: tegra: Start LTSSM after programming root port
  PCI: tegra: Move REFCLK pad settings out of phy_power_on()
  PCI: tegra: Retrain link for Gen2 speed
  PCI: tegra: Advertise AER capability
  PCI: tegra: Program UPHY electrical settings in Tegra210
  PCI: tegra: Enable opportunistic update FC and ACK
  PCI: tegra: Disable AFI dynamic clock gating
  PCI: tegra: Wait for DLLP to finish before entering L1 or L2
  PCI: tegra: Enable PCIe xclk clock clamping
  PCI: tegra: Add SW fixup for RAW violations
  PCI: tegra: Increase the deskew retry time
  PCI: tegra: Update flow control threshold in Tegra210

 drivers/pci/host/pci-tegra.c | 306 ++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 288 insertions(+), 18 deletions(-)

-- 
2.1.4

[PATCH 01/12] PCI: tegra: Start LTSSM after programming root port

[Manikanta Maddireddy]

This patch ensures that LTSSM is started (by deasserting pcie_xrst) only
after all the required root port register programming is completed.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/pci/host/pci-tegra.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 96e8038c3019..b41c60c7414c 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -1024,9 +1024,6 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
 		}
 	}
 
-	/* take the PCIe interface module out of reset */
-	reset_control_deassert(pcie->pcie_xrst);
-
 	/* finally enable PCIe */
 	value = afi_readl(pcie, AFI_CONFIGURATION);
 	value |= AFI_CONFIGURATION_EN_FPCI;
@@ -1065,7 +1062,6 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie)
 			dev_err(dev, "failed to power off PHY(s): %d\n", err);
 	}
 
-	reset_control_assert(pcie->pcie_xrst);
 	reset_control_assert(pcie->afi_rst);
 	reset_control_assert(pcie->pex_rst);
 
@@ -2116,7 +2112,12 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
 			 port->index, port->lanes);
 
 		tegra_pcie_port_enable(port);
+	}
 
+	/* take the PCIe interface module out of reset */
+	reset_control_deassert(pcie->pcie_xrst);
+
+	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
 		if (tegra_pcie_port_check_link(port))
 			continue;
 
-- 
2.1.4

[PATCH 02/12] PCI: tegra: Move REFCLK pad settings out of phy_power_on()

[Manikanta Maddireddy]

In Tegra186 PHY programming is done by BPMP-FW, so PHY calls are skipped
in driver. REFCLK pad settings are independent of PHY and should be
programmed by driver. So move REFCLK pad settings out of phy_power_on().
These pad settings improves REFCLK peak to peak amplitude.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/pci/host/pci-tegra.c | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index b41c60c7414c..2c64eb6cc3cc 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -910,7 +910,6 @@ static int tegra_pcie_port_phy_power_off(struct tegra_pcie_port *port)
 static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
 {
 	struct device *dev = pcie->dev;
-	const struct tegra_pcie_soc *soc = pcie->soc;
 	struct tegra_pcie_port *port;
 	int err;
 
@@ -936,12 +935,6 @@ static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
 		}
 	}
 
-	/* Configure the reference clock driver */
-	pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
-
-	if (soc->num_ports > 2)
-		pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
-
 	return 0;
 }
 
@@ -2049,6 +2042,17 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
 	return 0;
 }
 
+static void tegra_pcie_apply_pad_settings(struct tegra_pcie *pcie)
+{
+	const struct tegra_pcie_soc *soc = pcie->soc;
+
+	/* Configure the reference clock driver */
+	pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
+
+	if (soc->num_ports > 2)
+		pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
+}
+
 /*
  * FIXME: If there are no PCIe cards attached, then calling this function
  * can result in the increase of the bootup time as there are big timeout
@@ -2107,6 +2111,7 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
 	struct device *dev = pcie->dev;
 	struct tegra_pcie_port *port, *tmp;
 
+	tegra_pcie_apply_pad_settings(pcie);
 	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
 		dev_info(dev, "probing port %u, using %u lanes\n",
 			 port->index, port->lanes);
-- 
2.1.4

[PATCH 03/12] PCI: tegra: Retrain link for Gen2 speed

[Manikanta Maddireddy]

Tegra124, 132, 210 and 186 supports Gen2 link speed. After the link is up
in Gen1, set target link speed as Gen2 and retrain link. Link switches to
Gen2 speed if Gen2 capable end point is connected, else link stays in Gen1.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/pci/host/pci-tegra.c | 42 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 2c64eb6cc3cc..15df60e13a14 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -232,6 +232,8 @@
 #define PADS_REFCLK_CFG_PREDI_SHIFT		8  /* 11:8 */
 #define PADS_REFCLK_CFG_DRVI_SHIFT		12 /* 15:12 */
 
+#define LINK_RETRAIN_TIMEOUT HZ
+
 struct tegra_msi {
 	struct msi_controller chip;
 	DECLARE_BITMAP(used, INT_PCI_MSI_NR);
@@ -2133,6 +2135,42 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
 	}
 }
 
+static void tegra_pcie_change_link_speed(struct tegra_pcie *pcie,
+		struct pci_dev *pci_dev)
+{
+	struct device *dev = pcie->dev;
+	unsigned long start_jiffies;
+	unsigned short val;
+
+	/* Skip if the current device is not a root port */
+	if (pci_pcie_type(pci_dev) != PCI_EXP_TYPE_ROOT_PORT)
+		return;
+
+	pcie_capability_read_word(pci_dev, PCI_EXP_LNKCTL2, &val);
+	val &= ~PCI_EXP_LNKSTA_CLS;
+	val |= PCI_EXP_LNKSTA_CLS_5_0GB;
+	pcie_capability_write_word(pci_dev, PCI_EXP_LNKCTL2, val);
+
+	/* Retrain the link */
+	pcie_capability_read_word(pci_dev, PCI_EXP_LNKCTL, &val);
+	val |= PCI_EXP_LNKCTL_RL;
+	pcie_capability_write_word(pci_dev, PCI_EXP_LNKCTL, val);
+
+	start_jiffies = jiffies;
+	for (;;) {
+		pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &val);
+		if (!(val & PCI_EXP_LNKSTA_LT))
+			break;
+		if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
+			break;
+		usleep_range(2000, 3000);
+	}
+
+	if (val & PCI_EXP_LNKSTA_LT)
+		dev_err(dev, "link retrain of PCIe slot %u failed\n",
+				PCI_SLOT(pci_dev->devfn));
+}
+
 static const struct tegra_pcie_soc tegra20_pcie = {
 	.num_ports = 2,
 	.msi_base_shift = 0,
@@ -2334,6 +2372,7 @@ static int tegra_pcie_probe(struct platform_device *pdev)
 	struct pci_host_bridge *host;
 	struct tegra_pcie *pcie;
 	struct pci_bus *child;
+	struct pci_dev *pci_dev = NULL;
 	int err;
 
 	host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
@@ -2399,6 +2438,9 @@ static int tegra_pcie_probe(struct platform_device *pdev)
 
 	pci_bus_add_devices(host->bus);
 
+	for_each_pci_dev(pci_dev)
+		tegra_pcie_change_link_speed(pcie, pci_dev);
+
 	if (IS_ENABLED(CONFIG_DEBUG_FS)) {
 		err = tegra_pcie_debugfs_init(pcie);
 		if (err < 0)
-- 
2.1.4

Re: [PATCH 03/12] PCI: tegra: Retrain link for Gen2 speed

[Vidya Sagar]

On Saturday 28 October 2017 12:59 AM, Manikanta Maddireddy wrote:
> Tegra124, 132, 210 and 186 supports Gen2 link speed. After the link is up
> in Gen1, set target link speed as Gen2 and retrain link. Link switches to
> Gen2 speed if Gen2 capable end point is connected, else link stays in Gen1.
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
>   drivers/pci/host/pci-tegra.c | 42 ++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 42 insertions(+)
>
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index 2c64eb6cc3cc..15df60e13a14 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -232,6 +232,8 @@
>   #define PADS_REFCLK_CFG_PREDI_SHIFT		8  /* 11:8 */
>   #define PADS_REFCLK_CFG_DRVI_SHIFT		12 /* 15:12 */
>   
> +#define LINK_RETRAIN_TIMEOUT HZ
> +
>   struct tegra_msi {
>   	struct msi_controller chip;
>   	DECLARE_BITMAP(used, INT_PCI_MSI_NR);
> @@ -2133,6 +2135,42 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
>   	}
>   }
>   
> +static void tegra_pcie_change_link_speed(struct tegra_pcie *pcie,
> +		struct pci_dev *pci_dev)
> +{
> +	struct device *dev = pcie->dev;
> +	unsigned long start_jiffies;
> +	unsigned short val;
> +
> +	/* Skip if the current device is not a root port */
> +	if (pci_pcie_type(pci_dev) != PCI_EXP_TYPE_ROOT_PORT)
> +		return;
> +
> +	pcie_capability_read_word(pci_dev, PCI_EXP_LNKCTL2, &val);
> +	val &= ~PCI_EXP_LNKSTA_CLS;
> +	val |= PCI_EXP_LNKSTA_CLS_5_0GB;
> +	pcie_capability_write_word(pci_dev, PCI_EXP_LNKCTL2, val);
> +
> +	/* Retrain the link */
> +	pcie_capability_read_word(pci_dev, PCI_EXP_LNKCTL, &val);
> +	val |= PCI_EXP_LNKCTL_RL;
> +	pcie_capability_write_word(pci_dev, PCI_EXP_LNKCTL, val);
> +
> +	start_jiffies = jiffies;
> +	for (;;) {
> +		pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &val);
> +		if (!(val & PCI_EXP_LNKSTA_LT))
> +			break;
> +		if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
> +			break;
> +		usleep_range(2000, 3000);
> +	}
> +
> +	if (val & PCI_EXP_LNKSTA_LT)
> +		dev_err(dev, "link retrain of PCIe slot %u failed\n",
> +				PCI_SLOT(pci_dev->devfn));
> +}
> +
>   static const struct tegra_pcie_soc tegra20_pcie = {
>   	.num_ports = 2,
>   	.msi_base_shift = 0,
> @@ -2334,6 +2372,7 @@ static int tegra_pcie_probe(struct platform_device *pdev)
>   	struct pci_host_bridge *host;
>   	struct tegra_pcie *pcie;
>   	struct pci_bus *child;
> +	struct pci_dev *pci_dev = NULL;
>   	int err;
>   
>   	host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
> @@ -2399,6 +2438,9 @@ static int tegra_pcie_probe(struct platform_device *pdev)
>   
>   	pci_bus_add_devices(host->bus);
>   
> +	for_each_pci_dev(pci_dev)
> +		tegra_pcie_change_link_speed(pcie, pci_dev);
> +
Why can't we loop over only root ports using 'pcie->ports' like how it 
is done in tegra_pcie_enable_ports() ?
>   	if (IS_ENABLED(CONFIG_DEBUG_FS)) {
>   		err = tegra_pcie_debugfs_init(pcie);
>   		if (err < 0)

Re: [PATCH 03/12] PCI: tegra: Retrain link for Gen2 speed

[Vidya Sagar]

On Sunday 29 October 2017 03:04 PM, Vidya Sagar wrote:
>
>
> On Saturday 28 October 2017 12:59 AM, Manikanta Maddireddy wrote:
>> Tegra124, 132, 210 and 186 supports Gen2 link speed. After the link 
>> is up
>> in Gen1, set target link speed as Gen2 and retrain link. Link 
>> switches to
>> Gen2 speed if Gen2 capable end point is connected, else link stays in 
>> Gen1.
>>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>>   drivers/pci/host/pci-tegra.c | 42 
>> ++++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 42 insertions(+)
>>
>> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
>> index 2c64eb6cc3cc..15df60e13a14 100644
>> --- a/drivers/pci/host/pci-tegra.c
>> +++ b/drivers/pci/host/pci-tegra.c
>> @@ -232,6 +232,8 @@
>>   #define PADS_REFCLK_CFG_PREDI_SHIFT        8  /* 11:8 */
>>   #define PADS_REFCLK_CFG_DRVI_SHIFT        12 /* 15:12 */
>>   +#define LINK_RETRAIN_TIMEOUT HZ
>> +
>>   struct tegra_msi {
>>       struct msi_controller chip;
>>       DECLARE_BITMAP(used, INT_PCI_MSI_NR);
>> @@ -2133,6 +2135,42 @@ static void tegra_pcie_enable_ports(struct 
>> tegra_pcie *pcie)
>>       }
>>   }
>>   +static void tegra_pcie_change_link_speed(struct tegra_pcie *pcie,
>> +        struct pci_dev *pci_dev)
alignment issue
>> +{
>> +    struct device *dev = pcie->dev;
>> +    unsigned long start_jiffies;
>> +    unsigned short val;
>> +
>> +    /* Skip if the current device is not a root port */
>> +    if (pci_pcie_type(pci_dev) != PCI_EXP_TYPE_ROOT_PORT)
>> +        return;
>> +
>> +    pcie_capability_read_word(pci_dev, PCI_EXP_LNKCTL2, &val);
>> +    val &= ~PCI_EXP_LNKSTA_CLS;
>> +    val |= PCI_EXP_LNKSTA_CLS_5_0GB;
>> +    pcie_capability_write_word(pci_dev, PCI_EXP_LNKCTL2, val);
>> +
>> +    /* Retrain the link */
>> +    pcie_capability_read_word(pci_dev, PCI_EXP_LNKCTL, &val);
>> +    val |= PCI_EXP_LNKCTL_RL;
>> +    pcie_capability_write_word(pci_dev, PCI_EXP_LNKCTL, val);
>> +
>> +    start_jiffies = jiffies;
>> +    for (;;) {
>> +        pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &val);
>> +        if (!(val & PCI_EXP_LNKSTA_LT))
>> +            break;
>> +        if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
>> +            break;
>> +        usleep_range(2000, 3000);
>> +    }
>> +
>> +    if (val & PCI_EXP_LNKSTA_LT)
>> +        dev_err(dev, "link retrain of PCIe slot %u failed\n",
>> +                PCI_SLOT(pci_dev->devfn));
alignment issue
>> +}
>> +
>>   static const struct tegra_pcie_soc tegra20_pcie = {
>>       .num_ports = 2,
>>       .msi_base_shift = 0,
>> @@ -2334,6 +2372,7 @@ static int tegra_pcie_probe(struct 
>> platform_device *pdev)
>>       struct pci_host_bridge *host;
>>       struct tegra_pcie *pcie;
>>       struct pci_bus *child;
>> +    struct pci_dev *pci_dev = NULL;
>>       int err;
>>         host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
>> @@ -2399,6 +2438,9 @@ static int tegra_pcie_probe(struct 
>> platform_device *pdev)
>>         pci_bus_add_devices(host->bus);
>>   +    for_each_pci_dev(pci_dev)
>> +        tegra_pcie_change_link_speed(pcie, pci_dev);
>> +
> Why can't we loop over only root ports using 'pcie->ports' like how it 
> is done in tegra_pcie_enable_ports() ?
>>       if (IS_ENABLED(CONFIG_DEBUG_FS)) {
>>           err = tegra_pcie_debugfs_init(pcie);
>>           if (err < 0)
>

Re: [PATCH 03/12] PCI: tegra: Retrain link for Gen2 speed

[Manikanta Maddireddy]

On 29-Oct-17 3:04 PM, Vidya Sagar wrote:
> 
> 
> On Saturday 28 October 2017 12:59 AM, Manikanta Maddireddy wrote:
>> Tegra124, 132, 210 and 186 supports Gen2 link speed. After the link is up
>> in Gen1, set target link speed as Gen2 and retrain link. Link switches to
>> Gen2 speed if Gen2 capable end point is connected, else link stays in Gen1.
>>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>>   drivers/pci/host/pci-tegra.c | 42 ++++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 42 insertions(+)
>>
>> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
>> index 2c64eb6cc3cc..15df60e13a14 100644
>> --- a/drivers/pci/host/pci-tegra.c
>> +++ b/drivers/pci/host/pci-tegra.c
>> @@ -232,6 +232,8 @@
>>   #define PADS_REFCLK_CFG_PREDI_SHIFT        8  /* 11:8 */
>>   #define PADS_REFCLK_CFG_DRVI_SHIFT        12 /* 15:12 */
>>   +#define LINK_RETRAIN_TIMEOUT HZ
>> +
>>   struct tegra_msi {
>>       struct msi_controller chip;
>>       DECLARE_BITMAP(used, INT_PCI_MSI_NR);
>> @@ -2133,6 +2135,42 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
>>       }
>>   }
>>   +static void tegra_pcie_change_link_speed(struct tegra_pcie *pcie,
>> +        struct pci_dev *pci_dev)
>> +{
>> +    struct device *dev = pcie->dev;
>> +    unsigned long start_jiffies;
>> +    unsigned short val;
>> +
>> +    /* Skip if the current device is not a root port */
>> +    if (pci_pcie_type(pci_dev) != PCI_EXP_TYPE_ROOT_PORT)
>> +        return;
>> +
>> +    pcie_capability_read_word(pci_dev, PCI_EXP_LNKCTL2, &val);
>> +    val &= ~PCI_EXP_LNKSTA_CLS;
>> +    val |= PCI_EXP_LNKSTA_CLS_5_0GB;
>> +    pcie_capability_write_word(pci_dev, PCI_EXP_LNKCTL2, val);
>> +
>> +    /* Retrain the link */
>> +    pcie_capability_read_word(pci_dev, PCI_EXP_LNKCTL, &val);
>> +    val |= PCI_EXP_LNKCTL_RL;
>> +    pcie_capability_write_word(pci_dev, PCI_EXP_LNKCTL, val);
>> +
>> +    start_jiffies = jiffies;
>> +    for (;;) {
>> +        pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &val);
>> +        if (!(val & PCI_EXP_LNKSTA_LT))
>> +            break;
>> +        if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
>> +            break;
>> +        usleep_range(2000, 3000);
>> +    }
>> +
>> +    if (val & PCI_EXP_LNKSTA_LT)
>> +        dev_err(dev, "link retrain of PCIe slot %u failed\n",
>> +                PCI_SLOT(pci_dev->devfn));
>> +}
>> +
>>   static const struct tegra_pcie_soc tegra20_pcie = {
>>       .num_ports = 2,
>>       .msi_base_shift = 0,
>> @@ -2334,6 +2372,7 @@ static int tegra_pcie_probe(struct platform_device *pdev)
>>       struct pci_host_bridge *host;
>>       struct tegra_pcie *pcie;
>>       struct pci_bus *child;
>> +    struct pci_dev *pci_dev = NULL;
>>       int err;
>>         host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
>> @@ -2399,6 +2438,9 @@ static int tegra_pcie_probe(struct platform_device *pdev)
>>         pci_bus_add_devices(host->bus);
>>   +    for_each_pci_dev(pci_dev)
>> +        tegra_pcie_change_link_speed(pcie, pci_dev);
>> +
> Why can't we loop over only root ports using 'pcie->ports' like how it is done in tegra_pcie_enable_ports() ?
It can be done, but I chose use to pci subsystem calls & register defines so that it is easy understand.
>>       if (IS_ENABLED(CONFIG_DEBUG_FS)) {
>>           err = tegra_pcie_debugfs_init(pcie);
>>           if (err < 0)
> 

[PATCH 04/12] PCI: tegra: Advertise AER capability

[Manikanta Maddireddy]

Default root port settings hide AER capability. This patch enables the
advertisement of AER capability by root port.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/pci/host/pci-tegra.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 15df60e13a14..c0cd88103e9e 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -187,6 +187,9 @@
 #define RP_VEND_XP	0x00000f00
 #define  RP_VEND_XP_DL_UP	(1 << 30)
 
+#define RP_VEND_CTL1	0xf48
+#define  RP_VEND_CTL1_ERPT	(1 << 13)
+
 #define RP_VEND_CTL2 0x00000fa8
 #define  RP_VEND_CTL2_PCA_ENABLE (1 << 7)
 
@@ -2055,6 +2058,16 @@ static void tegra_pcie_apply_pad_settings(struct tegra_pcie *pcie)
 		pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
 }
 
+static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
+{
+	unsigned long value;
+
+	/* Enable AER capability */
+	value = readl(port->base + RP_VEND_CTL1);
+	value |= RP_VEND_CTL1_ERPT;
+	writel(value, port->base + RP_VEND_CTL1);
+}
+
 /*
  * FIXME: If there are no PCIe cards attached, then calling this function
  * can result in the increase of the bootup time as there are big timeout
@@ -2119,6 +2132,7 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
 			 port->index, port->lanes);
 
 		tegra_pcie_port_enable(port);
+		tegra_pcie_enable_rp_features(port);
 	}
 
 	/* take the PCIe interface module out of reset */
-- 
2.1.4

Re: [PATCH 04/12] PCI: tegra: Advertise AER capability

[Vidya Sagar]

On Saturday 28 October 2017 12:59 AM, Manikanta Maddireddy wrote:
> Default root port settings hide AER capability. This patch enables the
> advertisement of AER capability by root port.
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
>   drivers/pci/host/pci-tegra.c | 14 ++++++++++++++
>   1 file changed, 14 insertions(+)
>
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index 15df60e13a14..c0cd88103e9e 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -187,6 +187,9 @@
>   #define RP_VEND_XP	0x00000f00
>   #define  RP_VEND_XP_DL_UP	(1 << 30)
>   
> +#define RP_VEND_CTL1	0xf48
> +#define  RP_VEND_CTL1_ERPT	(1 << 13)
BIT macro is preferred here.
> +
>   #define RP_VEND_CTL2 0x00000fa8
>   #define  RP_VEND_CTL2_PCA_ENABLE (1 << 7)
>   
> @@ -2055,6 +2058,16 @@ static void tegra_pcie_apply_pad_settings(struct tegra_pcie *pcie)
>   		pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
>   }
>   
> +static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
> +{
> +	unsigned long value;
> +
> +	/* Enable AER capability */
> +	value = readl(port->base + RP_VEND_CTL1);
> +	value |= RP_VEND_CTL1_ERPT;
> +	writel(value, port->base + RP_VEND_CTL1);
> +}
> +
>   /*
>    * FIXME: If there are no PCIe cards attached, then calling this function
>    * can result in the increase of the bootup time as there are big timeout
> @@ -2119,6 +2132,7 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
>   			 port->index, port->lanes);
>   
>   		tegra_pcie_port_enable(port);
> +		tegra_pcie_enable_rp_features(port);
>   	}
>   
>   	/* take the PCIe interface module out of reset */

Re: [PATCH 04/12] PCI: tegra: Advertise AER capability

[Manikanta Maddireddy]

On 29-Oct-17 3:09 PM, Vidya Sagar wrote:
> 
> 
> On Saturday 28 October 2017 12:59 AM, Manikanta Maddireddy wrote:
>> Default root port settings hide AER capability. This patch enables the
>> advertisement of AER capability by root port.
>>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>>   drivers/pci/host/pci-tegra.c | 14 ++++++++++++++
>>   1 file changed, 14 insertions(+)
>>
>> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
>> index 15df60e13a14..c0cd88103e9e 100644
>> --- a/drivers/pci/host/pci-tegra.c
>> +++ b/drivers/pci/host/pci-tegra.c
>> @@ -187,6 +187,9 @@
>>   #define RP_VEND_XP    0x00000f00
>>   #define  RP_VEND_XP_DL_UP    (1 << 30)
>>   +#define RP_VEND_CTL1    0xf48
>> +#define  RP_VEND_CTL1_ERPT    (1 << 13)
> BIT macro is preferred here.
Left shift is used everywhere, so to be inline with that I used same format
>> +
>>   #define RP_VEND_CTL2 0x00000fa8
>>   #define  RP_VEND_CTL2_PCA_ENABLE (1 << 7)
>>   @@ -2055,6 +2058,16 @@ static void tegra_pcie_apply_pad_settings(struct tegra_pcie *pcie)
>>           pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
>>   }
>>   +static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
>> +{
>> +    unsigned long value;
>> +
>> +    /* Enable AER capability */
>> +    value = readl(port->base + RP_VEND_CTL1);
>> +    value |= RP_VEND_CTL1_ERPT;
>> +    writel(value, port->base + RP_VEND_CTL1);
>> +}
>> +
>>   /*
>>    * FIXME: If there are no PCIe cards attached, then calling this function
>>    * can result in the increase of the bootup time as there are big timeout
>> @@ -2119,6 +2132,7 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
>>                port->index, port->lanes);
>>             tegra_pcie_port_enable(port);
>> +        tegra_pcie_enable_rp_features(port);
>>       }
>>         /* take the PCIe interface module out of reset */
> 

[PATCH 05/12] PCI: tegra: Program UPHY electrical settings in Tegra210

[Manikanta Maddireddy]

UPHY electrical programming guidelines are documented in Tegra210 TRM.
Program these electrical settings for proper eye diagram in all link
speeds.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/pci/host/pci-tegra.c | 95 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 95 insertions(+)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index c0cd88103e9e..af34daf3c6a2 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -184,6 +184,30 @@
 
 #define AFI_PEXBIAS_CTRL_0		0x168
 
+#define RP_ECTL_2_R1	0xe84
+#define  RP_ECTL_2_R1_RX_CTLE_1C_MASK		0xffff
+
+#define RP_ECTL_4_R1	0xe8c
+#define  RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK	(0xffff << 16)
+
+#define RP_ECTL_5_R1	0xe90
+#define  RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK	0xffffffff
+
+#define RP_ECTL_6_R1	0xe94
+#define  RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK	0xffffffff
+
+#define RP_ECTL_2_R2	0xea4
+#define  RP_ECTL_2_R2_RX_CTLE_1C_MASK		0xffff
+
+#define RP_ECTL_4_R2	0xeac
+#define  RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK	(0xffff << 16)
+
+#define RP_ECTL_5_R2	0xeb0
+#define  RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK	0xffffffff
+
+#define RP_ECTL_6_R2	0xeb4
+#define  RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK	0xffffffff
+
 #define RP_VEND_XP	0x00000f00
 #define  RP_VEND_XP_DL_UP	(1 << 30)
 
@@ -254,6 +278,14 @@ struct tegra_pcie_soc {
 	u32 tx_ref_sel;
 	u32 pads_refclk_cfg0;
 	u32 pads_refclk_cfg1;
+	u32 rp_ectl_2_r1;
+	u32 rp_ectl_4_r1;
+	u32 rp_ectl_5_r1;
+	u32 rp_ectl_6_r1;
+	u32 rp_ectl_2_r2;
+	u32 rp_ectl_4_r2;
+	u32 rp_ectl_5_r2;
+	u32 rp_ectl_6_r2;
 	bool has_pex_clkreq_en;
 	bool has_pex_bias_ctrl;
 	bool has_intr_prsnt_sense;
@@ -261,6 +293,7 @@ struct tegra_pcie_soc {
 	bool has_gen2;
 	bool force_pca_enable;
 	bool program_uphy;
+	bool program_ectl_settings;
 };
 
 static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
@@ -2058,6 +2091,52 @@ static void tegra_pcie_apply_pad_settings(struct tegra_pcie *pcie)
 		pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
 }
 
+static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port)
+{
+	unsigned long value;
+	const struct tegra_pcie_soc *soc = port->pcie->soc;
+
+	value = readl(port->base + RP_ECTL_2_R1);
+	value &= ~RP_ECTL_2_R1_RX_CTLE_1C_MASK;
+	value |= soc->rp_ectl_2_r1;
+	writel(value, port->base + RP_ECTL_2_R1);
+
+	value = readl(port->base + RP_ECTL_4_R1);
+	value &= ~RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK;
+	value |= soc->rp_ectl_4_r1;
+	writel(value, port->base + RP_ECTL_4_R1);
+
+	value = readl(port->base + RP_ECTL_5_R1);
+	value &= ~RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK;
+	value |= soc->rp_ectl_5_r1;
+	writel(value, port->base + RP_ECTL_5_R1);
+
+	value = readl(port->base + RP_ECTL_6_R1);
+	value &= ~RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK;
+	value |= soc->rp_ectl_6_r1;
+	writel(value, port->base + RP_ECTL_6_R1);
+
+	value = readl(port->base + RP_ECTL_2_R2);
+	value &= ~RP_ECTL_2_R2_RX_CTLE_1C_MASK;
+	value |= soc->rp_ectl_2_r2;
+	writel(value, port->base + RP_ECTL_2_R2);
+
+	value = readl(port->base + RP_ECTL_4_R2);
+	value &= ~RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK;
+	value |= soc->rp_ectl_4_r2;
+	writel(value, port->base + RP_ECTL_4_R2);
+
+	value = readl(port->base + RP_ECTL_5_R2);
+	value &= ~RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK;
+	value |= soc->rp_ectl_5_r2;
+	writel(value, port->base + RP_ECTL_5_R2);
+
+	value = readl(port->base + RP_ECTL_6_R2);
+	value &= ~RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK;
+	value |= soc->rp_ectl_6_r2;
+	writel(value, port->base + RP_ECTL_6_R2);
+}
+
 static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
 {
 	unsigned long value;
@@ -2125,6 +2204,7 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
 {
 	struct device *dev = pcie->dev;
 	struct tegra_pcie_port *port, *tmp;
+	const struct tegra_pcie_soc *soc = pcie->soc;
 
 	tegra_pcie_apply_pad_settings(pcie);
 	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
@@ -2132,6 +2212,8 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
 			 port->index, port->lanes);
 
 		tegra_pcie_port_enable(port);
+		if (soc->program_ectl_settings)
+			tegra_pcie_program_ectl_settings(port);
 		tegra_pcie_enable_rp_features(port);
 	}
 
@@ -2198,6 +2280,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
 	.has_gen2 = false,
 	.force_pca_enable = false,
 	.program_uphy = true,
+	.program_ectl_settings = false,
 };
 
 static const struct tegra_pcie_soc tegra30_pcie = {
@@ -2214,6 +2297,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
 	.has_gen2 = false,
 	.force_pca_enable = false,
 	.program_uphy = true,
+	.program_ectl_settings = false,
 };
 
 static const struct tegra_pcie_soc tegra124_pcie = {
@@ -2229,6 +2313,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
 	.has_gen2 = true,
 	.force_pca_enable = false,
 	.program_uphy = true,
+	.program_ectl_settings = false,
 };
 
 static const struct tegra_pcie_soc tegra210_pcie = {
@@ -2237,6 +2322,14 @@ static const struct tegra_pcie_soc tegra210_pcie = {
 	.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
 	.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
 	.pads_refclk_cfg0 = 0x90b890b8,
+	.rp_ectl_2_r1 = 0x0000000f,
+	.rp_ectl_4_r1 = 0x00670000,
+	.rp_ectl_5_r1 = 0x55010000,
+	.rp_ectl_6_r1 = 0x00000001,
+	.rp_ectl_2_r2 = 0x0000008f,
+	.rp_ectl_4_r2 = 0x00c70000,
+	.rp_ectl_5_r2 = 0x55010000,
+	.rp_ectl_6_r2 = 0x00000001,
 	.has_pex_clkreq_en = true,
 	.has_pex_bias_ctrl = true,
 	.has_intr_prsnt_sense = true,
@@ -2244,6 +2337,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
 	.has_gen2 = true,
 	.force_pca_enable = true,
 	.program_uphy = true,
+	.program_ectl_settings = true,
 };
 
 static const struct tegra_pcie_soc tegra186_pcie = {
@@ -2260,6 +2354,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
 	.has_gen2 = true,
 	.force_pca_enable = false,
 	.program_uphy = false,
+	.program_ectl_settings = false,
 };
 
 static const struct of_device_id tegra_pcie_of_match[] = {
-- 
2.1.4

[PATCH 06/12] PCI: tegra: Enable opportunistic update FC and ACK

[Manikanta Maddireddy]

This patch ensures that DL sends pending ACKs and update FC packets when
link is idle instead of waiting for timers to expire which improves PCIe
bandwidth.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/pci/host/pci-tegra.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index af34daf3c6a2..27a8211c48b2 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -209,7 +209,9 @@
 #define  RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK	0xffffffff
 
 #define RP_VEND_XP	0x00000f00
-#define  RP_VEND_XP_DL_UP	(1 << 30)
+#define  RP_VEND_XP_DL_UP			(1 << 30)
+#define  RP_VEND_XP_OPPORTUNISTIC_ACK		(1 << 27)
+#define  RP_VEND_XP_OPPORTUNISTIC_UPDATEFC	(1 << 28)
 
 #define RP_VEND_CTL1	0xf48
 #define  RP_VEND_CTL1_ERPT	(1 << 13)
@@ -2147,6 +2149,16 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
 	writel(value, port->base + RP_VEND_CTL1);
 }
 
+static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
+{
+	unsigned long value;
+
+	/* Optimal settings to enhance bandwidth */
+	value = readl(port->base + RP_VEND_XP);
+	value |= RP_VEND_XP_OPPORTUNISTIC_ACK;
+	value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC;
+	writel(value, port->base + RP_VEND_XP);
+}
 /*
  * FIXME: If there are no PCIe cards attached, then calling this function
  * can result in the increase of the bootup time as there are big timeout
@@ -2215,6 +2227,7 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
 		if (soc->program_ectl_settings)
 			tegra_pcie_program_ectl_settings(port);
 		tegra_pcie_enable_rp_features(port);
+		tegra_pcie_apply_sw_fixup(port);
 	}
 
 	/* take the PCIe interface module out of reset */
-- 
2.1.4

Re: [PATCH 06/12] PCI: tegra: Enable opportunistic update FC and ACK

[Vidya Sagar]

On Saturday 28 October 2017 12:59 AM, Manikanta Maddireddy wrote:
> This patch ensures that DL sends pending ACKs and update FC packets when
> link is idle instead of waiting for timers to expire which improves PCIe
> bandwidth.
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
>   drivers/pci/host/pci-tegra.c | 15 ++++++++++++++-
>   1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index af34daf3c6a2..27a8211c48b2 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -209,7 +209,9 @@
>   #define  RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK	0xffffffff
>   
>   #define RP_VEND_XP	0x00000f00
> -#define  RP_VEND_XP_DL_UP	(1 << 30)
> +#define  RP_VEND_XP_DL_UP			(1 << 30)
> +#define  RP_VEND_XP_OPPORTUNISTIC_ACK		(1 << 27)
> +#define  RP_VEND_XP_OPPORTUNISTIC_UPDATEFC	(1 << 28)
>   
BIT macro is preferred here.
>   #define RP_VEND_CTL1	0xf48
>   #define  RP_VEND_CTL1_ERPT	(1 << 13)
> @@ -2147,6 +2149,16 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
>   	writel(value, port->base + RP_VEND_CTL1);
>   }
>   
> +static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
> +{
> +	unsigned long value;
> +
> +	/* Optimal settings to enhance bandwidth */
> +	value = readl(port->base + RP_VEND_XP);
> +	value |= RP_VEND_XP_OPPORTUNISTIC_ACK;
> +	value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC;
> +	writel(value, port->base + RP_VEND_XP);
> +}
>   /*
>    * FIXME: If there are no PCIe cards attached, then calling this function
>    * can result in the increase of the bootup time as there are big timeout
> @@ -2215,6 +2227,7 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
>   		if (soc->program_ectl_settings)
>   			tegra_pcie_program_ectl_settings(port);
>   		tegra_pcie_enable_rp_features(port);
> +		tegra_pcie_apply_sw_fixup(port);
>   	}
>   
>   	/* take the PCIe interface module out of reset */

Re: [PATCH 06/12] PCI: tegra: Enable opportunistic update FC and ACK

[Manikanta Maddireddy]

On 29-Oct-17 3:11 PM, Vidya Sagar wrote:
> 
> 
> On Saturday 28 October 2017 12:59 AM, Manikanta Maddireddy wrote:
>> This patch ensures that DL sends pending ACKs and update FC packets when
>> link is idle instead of waiting for timers to expire which improves PCIe
>> bandwidth.
>>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>>   drivers/pci/host/pci-tegra.c | 15 ++++++++++++++-
>>   1 file changed, 14 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
>> index af34daf3c6a2..27a8211c48b2 100644
>> --- a/drivers/pci/host/pci-tegra.c
>> +++ b/drivers/pci/host/pci-tegra.c
>> @@ -209,7 +209,9 @@
>>   #define  RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK    0xffffffff
>>     #define RP_VEND_XP    0x00000f00
>> -#define  RP_VEND_XP_DL_UP    (1 << 30)
>> +#define  RP_VEND_XP_DL_UP            (1 << 30)
>> +#define  RP_VEND_XP_OPPORTUNISTIC_ACK        (1 << 27)
>> +#define  RP_VEND_XP_OPPORTUNISTIC_UPDATEFC    (1 << 28)
>>   
> BIT macro is preferred here.
Left shift is used everywhere, so to be inline with that I used same format
>>   #define RP_VEND_CTL1    0xf48
>>   #define  RP_VEND_CTL1_ERPT    (1 << 13)
>> @@ -2147,6 +2149,16 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
>>       writel(value, port->base + RP_VEND_CTL1);
>>   }
>>   +static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
>> +{
>> +    unsigned long value;
>> +
>> +    /* Optimal settings to enhance bandwidth */
>> +    value = readl(port->base + RP_VEND_XP);
>> +    value |= RP_VEND_XP_OPPORTUNISTIC_ACK;
>> +    value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC;
>> +    writel(value, port->base + RP_VEND_XP);
>> +}
>>   /*
>>    * FIXME: If there are no PCIe cards attached, then calling this function
>>    * can result in the increase of the bootup time as there are big timeout
>> @@ -2215,6 +2227,7 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
>>           if (soc->program_ectl_settings)
>>               tegra_pcie_program_ectl_settings(port);
>>           tegra_pcie_enable_rp_features(port);
>> +        tegra_pcie_apply_sw_fixup(port);
>>       }
>>         /* take the PCIe interface module out of reset */
> 

[PATCH 07/12] PCI: tegra: Disable AFI dynamic clock gating

[Manikanta Maddireddy]

When there are 32 outstanding writes from AFI to memory, the outstanding
write counter overflows and indicates that there are "0" outstanding write
transactions. This outstanding write counter is used to generate IDLE
signal to dynamically gate the AFI clock.

When memory controller is under heavy load, its possible that write
completions will come back to AFI after long delay and AFI write counter
overflows. AFI clock gets gated even when there are outstanding
transactions towards memory controller resutling in system hang.

Disable dynamic clock gating of AFI clock to avoid system hang.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/pci/host/pci-tegra.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 27a8211c48b2..b8cac871712b 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -103,8 +103,9 @@
 #define AFI_MSI_EN_VEC6		0xa4
 #define AFI_MSI_EN_VEC7		0xa8
 
-#define AFI_CONFIGURATION		0xac
-#define  AFI_CONFIGURATION_EN_FPCI	(1 << 0)
+#define AFI_CONFIGURATION			0xac
+#define  AFI_CONFIGURATION_EN_FPCI		(1 << 0)
+#define  AFI_CONFIGURATION_CLKEN_OVERRIDE	(1 << 31)
 
 #define AFI_FPCI_ERROR_MASKS	0xb0
 
@@ -1057,9 +1058,10 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
 		}
 	}
 
-	/* finally enable PCIe */
+	/* Disable AFI dynamic clock gating and enable PCIe */
 	value = afi_readl(pcie, AFI_CONFIGURATION);
-	value |= AFI_CONFIGURATION_EN_FPCI;
+	value |= (AFI_CONFIGURATION_EN_FPCI |
+			AFI_CONFIGURATION_CLKEN_OVERRIDE);
 	afi_writel(pcie, value, AFI_CONFIGURATION);
 
 	value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
-- 
2.1.4

Re: [PATCH 07/12] PCI: tegra: Disable AFI dynamic clock gating

[Vidya Sagar]

On Saturday 28 October 2017 12:59 AM, Manikanta Maddireddy wrote:
> When there are 32 outstanding writes from AFI to memory, the outstanding
> write counter overflows and indicates that there are "0" outstanding write
> transactions. This outstanding write counter is used to generate IDLE
> signal to dynamically gate the AFI clock.
>
> When memory controller is under heavy load, its possible that write
> completions will come back to AFI after long delay and AFI write counter
> overflows. AFI clock gets gated even when there are outstanding
> transactions towards memory controller resutling in system hang.
>
> Disable dynamic clock gating of AFI clock to avoid system hang.
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
>   drivers/pci/host/pci-tegra.c | 10 ++++++----
>   1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index 27a8211c48b2..b8cac871712b 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -103,8 +103,9 @@
>   #define AFI_MSI_EN_VEC6		0xa4
>   #define AFI_MSI_EN_VEC7		0xa8
>   
> -#define AFI_CONFIGURATION		0xac
> -#define  AFI_CONFIGURATION_EN_FPCI	(1 << 0)
> +#define AFI_CONFIGURATION			0xac
> +#define  AFI_CONFIGURATION_EN_FPCI		(1 << 0)
> +#define  AFI_CONFIGURATION_CLKEN_OVERRIDE	(1 << 31)
BIT macro is preferred here.
>   
>   #define AFI_FPCI_ERROR_MASKS	0xb0
>   
> @@ -1057,9 +1058,10 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
>   		}
>   	}
>   
> -	/* finally enable PCIe */
> +	/* Disable AFI dynamic clock gating and enable PCIe */
>   	value = afi_readl(pcie, AFI_CONFIGURATION);
> -	value |= AFI_CONFIGURATION_EN_FPCI;
> +	value |= (AFI_CONFIGURATION_EN_FPCI |
> +			AFI_CONFIGURATION_CLKEN_OVERRIDE);
>   	afi_writel(pcie, value, AFI_CONFIGURATION);
>   
>   	value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |

Re: [PATCH 07/12] PCI: tegra: Disable AFI dynamic clock gating

[Manikanta Maddireddy]

On 29-Oct-17 3:12 PM, Vidya Sagar wrote:
> 
> 
> On Saturday 28 October 2017 12:59 AM, Manikanta Maddireddy wrote:
>> When there are 32 outstanding writes from AFI to memory, the outstanding
>> write counter overflows and indicates that there are "0" outstanding write
>> transactions. This outstanding write counter is used to generate IDLE
>> signal to dynamically gate the AFI clock.
>>
>> When memory controller is under heavy load, its possible that write
>> completions will come back to AFI after long delay and AFI write counter
>> overflows. AFI clock gets gated even when there are outstanding
>> transactions towards memory controller resutling in system hang.
>>
>> Disable dynamic clock gating of AFI clock to avoid system hang.
>>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>>   drivers/pci/host/pci-tegra.c | 10 ++++++----
>>   1 file changed, 6 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
>> index 27a8211c48b2..b8cac871712b 100644
>> --- a/drivers/pci/host/pci-tegra.c
>> +++ b/drivers/pci/host/pci-tegra.c
>> @@ -103,8 +103,9 @@
>>   #define AFI_MSI_EN_VEC6        0xa4
>>   #define AFI_MSI_EN_VEC7        0xa8
>>   -#define AFI_CONFIGURATION        0xac
>> -#define  AFI_CONFIGURATION_EN_FPCI    (1 << 0)
>> +#define AFI_CONFIGURATION            0xac
>> +#define  AFI_CONFIGURATION_EN_FPCI        (1 << 0)
>> +#define  AFI_CONFIGURATION_CLKEN_OVERRIDE    (1 << 31)
> BIT macro is preferred here.
Left shift is used everywhere, so to be inline with that I used same format
>>     #define AFI_FPCI_ERROR_MASKS    0xb0
>>   @@ -1057,9 +1058,10 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
>>           }
>>       }
>>   -    /* finally enable PCIe */
>> +    /* Disable AFI dynamic clock gating and enable PCIe */
>>       value = afi_readl(pcie, AFI_CONFIGURATION);
>> -    value |= AFI_CONFIGURATION_EN_FPCI;
>> +    value |= (AFI_CONFIGURATION_EN_FPCI |
>> +            AFI_CONFIGURATION_CLKEN_OVERRIDE);
>>       afi_writel(pcie, value, AFI_CONFIGURATION);
>>         value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
> 

RE: [PATCH 07/12] PCI: tegra: Disable AFI dynamic clock gating

[David Laight]

From: Manikanta Maddireddy
> Sent: 27 October 2017 20:29
> When there are 32 outstanding writes from AFI to memory, the outstanding
> write counter overflows and indicates that there are "0" outstanding write
> transactions. This outstanding write counter is used to generate IDLE
> signal to dynamically gate the AFI clock.
> 
> When memory controller is under heavy load, its possible that write
> completions will come back to AFI after long delay and AFI write counter
> overflows. AFI clock gets gated even when there are outstanding
> transactions towards memory controller resutling in system hang.
> 
> Disable dynamic clock gating of AFI clock to avoid system hang.

At least some of the above really ought to be comments in the code.
(and with the earlier fix for limiting the number of writes.)

	David

Re: [PATCH 07/12] PCI: tegra: Disable AFI dynamic clock gating

[Manikanta Maddireddy]

On 30-Oct-17 9:28 PM, David Laight wrote:
> From: Manikanta Maddireddy
>> Sent: 27 October 2017 20:29
>> When there are 32 outstanding writes from AFI to memory, the outstanding
>> write counter overflows and indicates that there are "0" outstanding write
>> transactions. This outstanding write counter is used to generate IDLE
>> signal to dynamically gate the AFI clock.
>>
>> When memory controller is under heavy load, its possible that write
>> completions will come back to AFI after long delay and AFI write counter
>> overflows. AFI clock gets gated even when there are outstanding
>> transactions towards memory controller resutling in system hang.
>>
>> Disable dynamic clock gating of AFI clock to avoid system hang.
> 
> At least some of the above really ought to be comments in the code.
> (and with the earlier fix for limiting the number of writes.)
> 
> 	David
> 

Ok, will take care of it in next version

[PATCH 08/12] PCI: tegra: Wait for DLLP to finish before entering L1 or L2

[Manikanta Maddireddy]

Set required bit to have LTSSM wait for DLLP to finish before entering L1
or L2. This avoids truncation of PM messages which results in receiver
errors.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/pci/host/pci-tegra.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index b8cac871712b..6028d5f3d5bb 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -217,6 +217,9 @@
 #define RP_VEND_CTL1	0xf48
 #define  RP_VEND_CTL1_ERPT	(1 << 13)
 
+#define RP_VEND_XP_BIST	0xf4c
+#define  RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE	(1 << 28)
+
 #define RP_VEND_CTL2 0x00000fa8
 #define  RP_VEND_CTL2_PCA_ENABLE (1 << 7)
 
@@ -2160,6 +2163,13 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
 	value |= RP_VEND_XP_OPPORTUNISTIC_ACK;
 	value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC;
 	writel(value, port->base + RP_VEND_XP);
+
+	/* LTSSM will wait for DLLP to finish before entering L1 or L2,
+	 * to avoid truncation of PM messages which results in receiver errors
+	 */
+	value = readl(port->base + RP_VEND_XP_BIST);
+	value |= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE;
+	writel(value, port->base + RP_VEND_XP_BIST);
 }
 /*
  * FIXME: If there are no PCIe cards attached, then calling this function
-- 
2.1.4

Re: [PATCH 08/12] PCI: tegra: Wait for DLLP to finish before entering L1 or L2

[Vidya Sagar]

On Saturday 28 October 2017 12:59 AM, Manikanta Maddireddy wrote:
> Set required bit to have LTSSM wait for DLLP to finish before entering L1
> or L2. This avoids truncation of PM messages which results in receiver
> errors.
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
>   drivers/pci/host/pci-tegra.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
>
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index b8cac871712b..6028d5f3d5bb 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -217,6 +217,9 @@
>   #define RP_VEND_CTL1	0xf48
>   #define  RP_VEND_CTL1_ERPT	(1 << 13)
>   
> +#define RP_VEND_XP_BIST	0xf4c
> +#define  RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE	(1 << 28)
> +
BIT macro is preferred here.
>   #define RP_VEND_CTL2 0x00000fa8
>   #define  RP_VEND_CTL2_PCA_ENABLE (1 << 7)
>   
> @@ -2160,6 +2163,13 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
>   	value |= RP_VEND_XP_OPPORTUNISTIC_ACK;
>   	value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC;
>   	writel(value, port->base + RP_VEND_XP);
> +
> +	/* LTSSM will wait for DLLP to finish before entering L1 or L2,
> +	 * to avoid truncation of PM messages which results in receiver errors
> +	 */
> +	value = readl(port->base + RP_VEND_XP_BIST);
> +	value |= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE;
> +	writel(value, port->base + RP_VEND_XP_BIST);
>   }
>   /*
>    * FIXME: If there are no PCIe cards attached, then calling this function

Re: [PATCH 08/12] PCI: tegra: Wait for DLLP to finish before entering L1 or L2

[Manikanta Maddireddy]

On 29-Oct-17 3:12 PM, Vidya Sagar wrote:
> 
> 
> On Saturday 28 October 2017 12:59 AM, Manikanta Maddireddy wrote:
>> Set required bit to have LTSSM wait for DLLP to finish before entering L1
>> or L2. This avoids truncation of PM messages which results in receiver
>> errors.
>>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>>   drivers/pci/host/pci-tegra.c | 10 ++++++++++
>>   1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
>> index b8cac871712b..6028d5f3d5bb 100644
>> --- a/drivers/pci/host/pci-tegra.c
>> +++ b/drivers/pci/host/pci-tegra.c
>> @@ -217,6 +217,9 @@
>>   #define RP_VEND_CTL1    0xf48
>>   #define  RP_VEND_CTL1_ERPT    (1 << 13)
>>   +#define RP_VEND_XP_BIST    0xf4c
>> +#define  RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE    (1 << 28)
>> +
> BIT macro is preferred here.
Left shift is used everywhere, so to be inline with that I used same format
>>   #define RP_VEND_CTL2 0x00000fa8
>>   #define  RP_VEND_CTL2_PCA_ENABLE (1 << 7)
>>   @@ -2160,6 +2163,13 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
>>       value |= RP_VEND_XP_OPPORTUNISTIC_ACK;
>>       value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC;
>>       writel(value, port->base + RP_VEND_XP);
>> +
>> +    /* LTSSM will wait for DLLP to finish before entering L1 or L2,
>> +     * to avoid truncation of PM messages which results in receiver errors
>> +     */
>> +    value = readl(port->base + RP_VEND_XP_BIST);
>> +    value |= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE;
>> +    writel(value, port->base + RP_VEND_XP_BIST);
>>   }
>>   /*
>>    * FIXME: If there are no PCIe cards attached, then calling this function
> 

[PATCH 09/12] PCI: tegra: Enable PCIe xclk clock clamping

[Manikanta Maddireddy]

This patch enables PCIe xlck clock clamping by pad control. Pad control
asserts UPHY lane sleep signal when L1 entry signal received from PCIe.
UPHY sleep signal assertion is done per lane. Default clamp threshold
margin is not enough to assert all UPHY lane sleep signals. Increase
the clamp threshold in Tegra124, 132, 210 and 186.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/pci/host/pci-tegra.c | 28 ++++++++++++++++++++++++++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 6028d5f3d5bb..8fbc5950785a 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -224,8 +224,14 @@
 #define  RP_VEND_CTL2_PCA_ENABLE (1 << 7)
 
 #define RP_PRIV_MISC	0x00000fe0
-#define  RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0)
-#define  RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0)
+#define  RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT		(0xe << 0)
+#define  RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT		(0xf << 0)
+#define  RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK	(0x7f << 16)
+#define  RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD		(0xf << 16)
+#define  RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE		(1 << 23)
+#define  RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK	(0x7f << 24)
+#define  RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD		(0xf << 24)
+#define  RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE		(1 << 31)
 
 #define RP_LINK_CONTROL_STATUS			0x00000090
 #define  RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE	0x20000000
@@ -300,6 +306,7 @@ struct tegra_pcie_soc {
 	bool force_pca_enable;
 	bool program_uphy;
 	bool program_ectl_settings;
+	bool update_clamp_threshold;
 };
 
 static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
@@ -2156,6 +2163,7 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
 
 static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
 {
+	const struct tegra_pcie_soc *soc = port->pcie->soc;
 	unsigned long value;
 
 	/* Optimal settings to enhance bandwidth */
@@ -2170,6 +2178,17 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
 	value = readl(port->base + RP_VEND_XP_BIST);
 	value |= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE;
 	writel(value, port->base + RP_VEND_XP_BIST);
+
+	value = readl(port->base + RP_PRIV_MISC);
+	value |= (RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE |
+			 RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE);
+	if (soc->update_clamp_threshold) {
+		value &= ~(RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK |
+				RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK);
+		value |= (RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD |
+				RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD);
+	}
+	writel(value, port->base + RP_PRIV_MISC);
 }
 /*
  * FIXME: If there are no PCIe cards attached, then calling this function
@@ -2306,6 +2325,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
 	.force_pca_enable = false,
 	.program_uphy = true,
 	.program_ectl_settings = false,
+	.update_clamp_threshold = false,
 };
 
 static const struct tegra_pcie_soc tegra30_pcie = {
@@ -2323,6 +2343,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
 	.force_pca_enable = false,
 	.program_uphy = true,
 	.program_ectl_settings = false,
+	.update_clamp_threshold = false,
 };
 
 static const struct tegra_pcie_soc tegra124_pcie = {
@@ -2339,6 +2360,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
 	.force_pca_enable = false,
 	.program_uphy = true,
 	.program_ectl_settings = false,
+	.update_clamp_threshold = true,
 };
 
 static const struct tegra_pcie_soc tegra210_pcie = {
@@ -2363,6 +2385,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
 	.force_pca_enable = true,
 	.program_uphy = true,
 	.program_ectl_settings = true,
+	.update_clamp_threshold = true,
 };
 
 static const struct tegra_pcie_soc tegra186_pcie = {
@@ -2380,6 +2403,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
 	.force_pca_enable = false,
 	.program_uphy = false,
 	.program_ectl_settings = false,
+	.update_clamp_threshold = false,
 };
 
 static const struct of_device_id tegra_pcie_of_match[] = {
-- 
2.1.4

Re: [PATCH 09/12] PCI: tegra: Enable PCIe xclk clock clamping

[Vidya Sagar]

On Saturday 28 October 2017 12:59 AM, Manikanta Maddireddy wrote:
> This patch enables PCIe xlck clock clamping by pad control. Pad control
> asserts UPHY lane sleep signal when L1 entry signal received from PCIe.
> UPHY sleep signal assertion is done per lane. Default clamp threshold
> margin is not enough to assert all UPHY lane sleep signals. Increase
> the clamp threshold in Tegra124, 132, 210 and 186.
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
>   drivers/pci/host/pci-tegra.c | 28 ++++++++++++++++++++++++++--
>   1 file changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index 6028d5f3d5bb..8fbc5950785a 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -224,8 +224,14 @@
>   #define  RP_VEND_CTL2_PCA_ENABLE (1 << 7)
>   
>   #define RP_PRIV_MISC	0x00000fe0
> -#define  RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0)
> -#define  RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0)
> +#define  RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT		(0xe << 0)
> +#define  RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT		(0xf << 0)
> +#define  RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK	(0x7f << 16)
> +#define  RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD		(0xf << 16)
> +#define  RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE		(1 << 23)
> +#define  RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK	(0x7f << 24)
> +#define  RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD		(0xf << 24)
> +#define  RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE		(1 << 31)
>   
BIT macro is preferred here.
>   #define RP_LINK_CONTROL_STATUS			0x00000090
>   #define  RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE	0x20000000
> @@ -300,6 +306,7 @@ struct tegra_pcie_soc {
>   	bool force_pca_enable;
>   	bool program_uphy;
>   	bool program_ectl_settings;
> +	bool update_clamp_threshold;
>   };
>   
>   static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
> @@ -2156,6 +2163,7 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
>   
>   static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
>   {
> +	const struct tegra_pcie_soc *soc = port->pcie->soc;
>   	unsigned long value;
>   
>   	/* Optimal settings to enhance bandwidth */
> @@ -2170,6 +2178,17 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
>   	value = readl(port->base + RP_VEND_XP_BIST);
>   	value |= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE;
>   	writel(value, port->base + RP_VEND_XP_BIST);
> +
> +	value = readl(port->base + RP_PRIV_MISC);
> +	value |= (RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE |
> +			 RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE);
> +	if (soc->update_clamp_threshold) {
> +		value &= ~(RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK |
> +				RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK);
> +		value |= (RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD |
> +				RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD);
> +	}
> +	writel(value, port->base + RP_PRIV_MISC);
>   }
>   /*
>    * FIXME: If there are no PCIe cards attached, then calling this function
> @@ -2306,6 +2325,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
>   	.force_pca_enable = false,
>   	.program_uphy = true,
>   	.program_ectl_settings = false,
> +	.update_clamp_threshold = false,
>   };
>   
>   static const struct tegra_pcie_soc tegra30_pcie = {
> @@ -2323,6 +2343,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
>   	.force_pca_enable = false,
>   	.program_uphy = true,
>   	.program_ectl_settings = false,
> +	.update_clamp_threshold = false,
>   };
>   
>   static const struct tegra_pcie_soc tegra124_pcie = {
> @@ -2339,6 +2360,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
>   	.force_pca_enable = false,
>   	.program_uphy = true,
>   	.program_ectl_settings = false,
> +	.update_clamp_threshold = true,
>   };
>   
>   static const struct tegra_pcie_soc tegra210_pcie = {
> @@ -2363,6 +2385,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
>   	.force_pca_enable = true,
>   	.program_uphy = true,
>   	.program_ectl_settings = true,
> +	.update_clamp_threshold = true,
>   };
>   
>   static const struct tegra_pcie_soc tegra186_pcie = {
> @@ -2380,6 +2403,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
>   	.force_pca_enable = false,
>   	.program_uphy = false,
>   	.program_ectl_settings = false,
> +	.update_clamp_threshold = false,
>   };
>   
>   static const struct of_device_id tegra_pcie_of_match[] = {

Re: [PATCH 09/12] PCI: tegra: Enable PCIe xclk clock clamping

[Manikanta Maddireddy]

On 29-Oct-17 3:13 PM, Vidya Sagar wrote:
> 
> 
> On Saturday 28 October 2017 12:59 AM, Manikanta Maddireddy wrote:
>> This patch enables PCIe xlck clock clamping by pad control. Pad control
>> asserts UPHY lane sleep signal when L1 entry signal received from PCIe.
>> UPHY sleep signal assertion is done per lane. Default clamp threshold
>> margin is not enough to assert all UPHY lane sleep signals. Increase
>> the clamp threshold in Tegra124, 132, 210 and 186.
>>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>>   drivers/pci/host/pci-tegra.c | 28 ++++++++++++++++++++++++++--
>>   1 file changed, 26 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
>> index 6028d5f3d5bb..8fbc5950785a 100644
>> --- a/drivers/pci/host/pci-tegra.c
>> +++ b/drivers/pci/host/pci-tegra.c
>> @@ -224,8 +224,14 @@
>>   #define  RP_VEND_CTL2_PCA_ENABLE (1 << 7)
>>     #define RP_PRIV_MISC    0x00000fe0
>> -#define  RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0)
>> -#define  RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0)
>> +#define  RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT        (0xe << 0)
>> +#define  RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT        (0xf << 0)
>> +#define  RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK    (0x7f << 16)
>> +#define  RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD        (0xf << 16)
>> +#define  RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE        (1 << 23)
>> +#define  RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK    (0x7f << 24)
>> +#define  RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD        (0xf << 24)
>> +#define  RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE        (1 << 31)
>>   
> BIT macro is preferred here.
Left shift is used everywhere, so to be inline with that I used same format
>>   #define RP_LINK_CONTROL_STATUS            0x00000090
>>   #define  RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE    0x20000000
>> @@ -300,6 +306,7 @@ struct tegra_pcie_soc {
>>       bool force_pca_enable;
>>       bool program_uphy;
>>       bool program_ectl_settings;
>> +    bool update_clamp_threshold;
>>   };
>>     static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
>> @@ -2156,6 +2163,7 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
>>     static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
>>   {
>> +    const struct tegra_pcie_soc *soc = port->pcie->soc;
>>       unsigned long value;
>>         /* Optimal settings to enhance bandwidth */
>> @@ -2170,6 +2178,17 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
>>       value = readl(port->base + RP_VEND_XP_BIST);
>>       value |= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE;
>>       writel(value, port->base + RP_VEND_XP_BIST);
>> +
>> +    value = readl(port->base + RP_PRIV_MISC);
>> +    value |= (RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE |
>> +             RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE);
>> +    if (soc->update_clamp_threshold) {
>> +        value &= ~(RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK |
>> +                RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK);
>> +        value |= (RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD |
>> +                RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD);
>> +    }
>> +    writel(value, port->base + RP_PRIV_MISC);
>>   }
>>   /*
>>    * FIXME: If there are no PCIe cards attached, then calling this function
>> @@ -2306,6 +2325,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
>>       .force_pca_enable = false,
>>       .program_uphy = true,
>>       .program_ectl_settings = false,
>> +    .update_clamp_threshold = false,
>>   };
>>     static const struct tegra_pcie_soc tegra30_pcie = {
>> @@ -2323,6 +2343,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
>>       .force_pca_enable = false,
>>       .program_uphy = true,
>>       .program_ectl_settings = false,
>> +    .update_clamp_threshold = false,
>>   };
>>     static const struct tegra_pcie_soc tegra124_pcie = {
>> @@ -2339,6 +2360,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
>>       .force_pca_enable = false,
>>       .program_uphy = true,
>>       .program_ectl_settings = false,
>> +    .update_clamp_threshold = true,
>>   };
>>     static const struct tegra_pcie_soc tegra210_pcie = {
>> @@ -2363,6 +2385,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
>>       .force_pca_enable = true,
>>       .program_uphy = true,
>>       .program_ectl_settings = true,
>> +    .update_clamp_threshold = true,
>>   };
>>     static const struct tegra_pcie_soc tegra186_pcie = {
>> @@ -2380,6 +2403,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
>>       .force_pca_enable = false,
>>       .program_uphy = false,
>>       .program_ectl_settings = false,
>> +    .update_clamp_threshold = false,
>>   };
>>     static const struct of_device_id tegra_pcie_of_match[] = {
> 

[PATCH 10/12] PCI: tegra: Add SW fixup for RAW violations

[Manikanta Maddireddy]

The logic which blocks read requests till AFI gets ACK for all outstanding
MC writes does not behave correctly when number of outstanding write
becomes more than 32.

SW fixup to prevent this issue is to limit outstanding posted writes and
tweak updateFC timer threshold.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/pci/host/pci-tegra.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 8fbc5950785a..9680bf7d0a95 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -185,6 +185,13 @@
 
 #define AFI_PEXBIAS_CTRL_0		0x168
 
+#define RP_PRIV_XP_DL	0x494
+#define  RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD	(0x1ff << 1)
+
+#define RP_RX_HDR_LIMIT	0xe00
+#define  RP_RX_HDR_LIMIT_PW_MASK	(0xff << 8)
+#define  RP_RX_HDR_LIMIT_PW		(0x0e << 8)
+
 #define RP_ECTL_2_R1	0xe84
 #define  RP_ECTL_2_R1_RX_CTLE_1C_MASK		0xffff
 
@@ -213,6 +220,7 @@
 #define  RP_VEND_XP_DL_UP			(1 << 30)
 #define  RP_VEND_XP_OPPORTUNISTIC_ACK		(1 << 27)
 #define  RP_VEND_XP_OPPORTUNISTIC_UPDATEFC	(1 << 28)
+#define  RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK	(0xff << 18)
 
 #define RP_VEND_CTL1	0xf48
 #define  RP_VEND_CTL1_ERPT	(1 << 13)
@@ -307,6 +315,7 @@ struct tegra_pcie_soc {
 	bool program_uphy;
 	bool program_ectl_settings;
 	bool update_clamp_threshold;
+	bool RAW_violation_fixup;
 };
 
 static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
@@ -2189,6 +2198,22 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
 				RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD);
 	}
 	writel(value, port->base + RP_PRIV_MISC);
+
+	/* Fixup for read after write violation in T124 & T132 platforms */
+	if (soc->RAW_violation_fixup) {
+		value = readl(port->base + RP_RX_HDR_LIMIT);
+		value &= ~RP_RX_HDR_LIMIT_PW_MASK;
+		value |= RP_RX_HDR_LIMIT_PW;
+		writel(value, port->base + RP_RX_HDR_LIMIT);
+
+		value = readl(port->base + RP_PRIV_XP_DL);
+		value |= RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD;
+		writel(value, port->base + RP_PRIV_XP_DL);
+
+		value = readl(port->base + RP_VEND_XP);
+		value |= RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK;
+		writel(value, port->base + RP_VEND_XP);
+	}
 }
 /*
  * FIXME: If there are no PCIe cards attached, then calling this function
@@ -2326,6 +2351,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
 	.program_uphy = true,
 	.program_ectl_settings = false,
 	.update_clamp_threshold = false,
+	.RAW_violation_fixup = false,
 };
 
 static const struct tegra_pcie_soc tegra30_pcie = {
@@ -2344,6 +2370,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
 	.program_uphy = true,
 	.program_ectl_settings = false,
 	.update_clamp_threshold = false,
+	.RAW_violation_fixup = false,
 };
 
 static const struct tegra_pcie_soc tegra124_pcie = {
@@ -2361,6 +2388,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
 	.program_uphy = true,
 	.program_ectl_settings = false,
 	.update_clamp_threshold = true,
+	.RAW_violation_fixup = true,
 };
 
 static const struct tegra_pcie_soc tegra210_pcie = {
@@ -2386,6 +2414,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
 	.program_uphy = true,
 	.program_ectl_settings = true,
 	.update_clamp_threshold = true,
+	.RAW_violation_fixup = false,
 };
 
 static const struct tegra_pcie_soc tegra186_pcie = {
@@ -2404,6 +2433,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
 	.program_uphy = false,
 	.program_ectl_settings = false,
 	.update_clamp_threshold = false,
+	.RAW_violation_fixup = false,
 };
 
 static const struct of_device_id tegra_pcie_of_match[] = {
-- 
2.1.4

[PATCH 11/12] PCI: tegra: Increase the deskew retry time

[Manikanta Maddireddy]

Some times Gen2 to Gen1 link speed switching fails due to instability in
deskew logic on lane0 in Tegra210. Increase the deskew retry time to
resolve this issue.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/pci/host/pci-tegra.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 9680bf7d0a95..db1ce74ba64a 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -222,6 +222,10 @@
 #define  RP_VEND_XP_OPPORTUNISTIC_UPDATEFC	(1 << 28)
 #define  RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK	(0xff << 18)
 
+#define RP_VEND_CTL0	0xf44
+#define  RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK	(0xf << 12)
+#define  RP_VEND_CTL0_DSK_RST_PULSE_WIDTH	(0x9 << 12)
+
 #define RP_VEND_CTL1	0xf48
 #define  RP_VEND_CTL1_ERPT	(1 << 13)
 
@@ -316,6 +320,7 @@ struct tegra_pcie_soc {
 	bool program_ectl_settings;
 	bool update_clamp_threshold;
 	bool RAW_violation_fixup;
+	bool program_deskew_time;
 };
 
 static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
@@ -2214,6 +2219,16 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
 		value |= RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK;
 		writel(value, port->base + RP_VEND_XP);
 	}
+
+	/* Tune deskew retry time to take care of Gen2 -> Gen1
+	 * link speed change error in corner cases
+	 */
+	if (soc->program_deskew_time) {
+		value = readl(port->base + RP_VEND_CTL0);
+		value &= ~RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK;
+		value |= RP_VEND_CTL0_DSK_RST_PULSE_WIDTH;
+		writel(value, port->base + RP_VEND_CTL0);
+	}
 }
 /*
  * FIXME: If there are no PCIe cards attached, then calling this function
@@ -2352,6 +2367,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
 	.program_ectl_settings = false,
 	.update_clamp_threshold = false,
 	.RAW_violation_fixup = false,
+	.program_deskew_time = false,
 };
 
 static const struct tegra_pcie_soc tegra30_pcie = {
@@ -2371,6 +2387,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
 	.program_ectl_settings = false,
 	.update_clamp_threshold = false,
 	.RAW_violation_fixup = false,
+	.program_deskew_time = false,
 };
 
 static const struct tegra_pcie_soc tegra124_pcie = {
@@ -2389,6 +2406,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
 	.program_ectl_settings = false,
 	.update_clamp_threshold = true,
 	.RAW_violation_fixup = true,
+	.program_deskew_time = false,
 };
 
 static const struct tegra_pcie_soc tegra210_pcie = {
@@ -2415,6 +2433,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
 	.program_ectl_settings = true,
 	.update_clamp_threshold = true,
 	.RAW_violation_fixup = false,
+	.program_deskew_time = true,
 };
 
 static const struct tegra_pcie_soc tegra186_pcie = {
@@ -2434,6 +2453,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
 	.program_ectl_settings = false,
 	.update_clamp_threshold = false,
 	.RAW_violation_fixup = false,
+	.program_deskew_time = false,
 };
 
 static const struct of_device_id tegra_pcie_of_match[] = {
-- 
2.1.4

[PATCH 12/12] PCI: tegra: Update flow control threshold in Tegra210

[Manikanta Maddireddy]

Recommended update FC threshold in Tegra210 is 0x60 for best performance
of x1 link. Setting this to 0x60 provides the best balance between number
of UpdateFC and read data sent over the link.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 drivers/pci/host/pci-tegra.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index db1ce74ba64a..da5f4998f149 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -221,6 +221,7 @@
 #define  RP_VEND_XP_OPPORTUNISTIC_ACK		(1 << 27)
 #define  RP_VEND_XP_OPPORTUNISTIC_UPDATEFC	(1 << 28)
 #define  RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK	(0xff << 18)
+#define  RP_VEND_XP_UPDATE_FC_THRESHOLD_T210	(0x60 << 18)
 
 #define RP_VEND_CTL0	0xf44
 #define  RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK	(0xf << 12)
@@ -321,6 +322,7 @@ struct tegra_pcie_soc {
 	bool update_clamp_threshold;
 	bool RAW_violation_fixup;
 	bool program_deskew_time;
+	bool updateFC_threshold;
 };
 
 static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
@@ -2229,6 +2231,13 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
 		value |= RP_VEND_CTL0_DSK_RST_PULSE_WIDTH;
 		writel(value, port->base + RP_VEND_CTL0);
 	}
+
+	if (soc->updateFC_threshold) {
+		value = readl(port->base + RP_VEND_XP);
+		value &= ~RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK;
+		value |= RP_VEND_XP_UPDATE_FC_THRESHOLD_T210;
+		writel(value, port->base + RP_VEND_XP);
+	}
 }
 /*
  * FIXME: If there are no PCIe cards attached, then calling this function
@@ -2368,6 +2377,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
 	.update_clamp_threshold = false,
 	.RAW_violation_fixup = false,
 	.program_deskew_time = false,
+	.updateFC_threshold = false,
 };
 
 static const struct tegra_pcie_soc tegra30_pcie = {
@@ -2388,6 +2398,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
 	.update_clamp_threshold = false,
 	.RAW_violation_fixup = false,
 	.program_deskew_time = false,
+	.updateFC_threshold = false,
 };
 
 static const struct tegra_pcie_soc tegra124_pcie = {
@@ -2407,6 +2418,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
 	.update_clamp_threshold = true,
 	.RAW_violation_fixup = true,
 	.program_deskew_time = false,
+	.updateFC_threshold = false,
 };
 
 static const struct tegra_pcie_soc tegra210_pcie = {
@@ -2434,6 +2446,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
 	.update_clamp_threshold = true,
 	.RAW_violation_fixup = false,
 	.program_deskew_time = true,
+	.updateFC_threshold = true,
 };
 
 static const struct tegra_pcie_soc tegra186_pcie = {
@@ -2454,6 +2467,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
 	.update_clamp_threshold = false,
 	.RAW_violation_fixup = false,
 	.program_deskew_time = false,
+	.updateFC_threshold = false,
 };
 
 static const struct of_device_id tegra_pcie_of_match[] = {
-- 
2.1.4