From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: superm1@kernel.org
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Mathias Nyman <mathias.nyman@intel.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
"open list : PCI SUBSYSTEM" <linux-pci@vger.kernel.org>,
open list <linux-kernel@vger.kernel.org>,
"open list : USB XHCI DRIVER" <linux-usb@vger.kernel.org>,
Daniel Drake <drake@endlessos.org>, Gary Li <Gary.Li@amd.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Mario Limonciello <mario.limonciello@amd.com>
Subject: Re: [PATCH v2 1/4] PCI: Check PCI_PM_CTRL in pci_dev_wait()
Date: Thu, 11 Jul 2024 18:07:57 +0300 (EEST) [thread overview]
Message-ID: <15091369-fc5c-af2d-7591-e1732097e84c@linux.intel.com> (raw)
In-Reply-To: <20240710205838.2413465-2-superm1@kernel.org>
On Wed, 10 Jul 2024, superm1@kernel.org wrote:
> From: Mario Limonciello <mario.limonciello@amd.com>
>
> A device that has gone through a reset may return a value in PCI_COMMAND
> but that doesn't mean it's finished transitioning to D0. On devices that
> support power management explicitly check PCI_PM_CTRL on everything but
> system resume to ensure the transition happened.
>
> Devices that don't support power management and system resume will
> continue to use PCI_COMMAND.
>
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
> drivers/pci/pci.c | 27 ++++++++++++++++++++-------
> 1 file changed, 20 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 35fb1f17a589c..4ad02ad640518 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -1270,21 +1270,34 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
> * the read (except when CRS SV is enabled and the read was for the
> * Vendor ID; in that case it synthesizes 0x0001 data).
> *
> - * Wait for the device to return a non-CRS completion. Read the
> - * Command register instead of Vendor ID so we don't have to
> - * contend with the CRS SV value.
> + * Wait for the device to return a non-CRS completion. On devices
> + * that support PM control and on waits that aren't part of system
> + * resume read the PM control register to ensure the device has
> + * transitioned to D0. On devices that don't support PM control,
> + * or during system resume read the command register to instead of
> + * Vendor ID so we don't have to contend with the CRS SV value.
> */
> for (;;) {
> - u32 id;
>
> if (pci_dev_is_disconnected(dev)) {
> pci_dbg(dev, "disconnected; not waiting\n");
> return -ENOTTY;
> }
>
> - pci_read_config_dword(dev, PCI_COMMAND, &id);
> - if (!PCI_POSSIBLE_ERROR(id))
> - break;
> + if (dev->pm_cap && strcmp(reset_type, "resume") != 0) {
Comparing to a string makes me feel reset_type should be changed to
something that allows direct compare and those values only mapped into
string while printing it.
--
i.
> + u16 pmcsr;
> +
> + pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
> + if (!PCI_POSSIBLE_ERROR(pmcsr) &&
> + (pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D0)
> + break;
> + } else {
> + u32 id;
> +
> + pci_read_config_dword(dev, PCI_COMMAND, &id);
> + if (!PCI_POSSIBLE_ERROR(id))
> + break;
> + }
>
> if (delay > timeout) {
> pci_warn(dev, "not ready %dms after %s; giving up\n",
>
next prev parent reply other threads:[~2024-07-11 15:08 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-10 20:58 [PATCH v2 0/4] Verify devices transition from D3cold to D0 superm1
2024-07-10 20:58 ` [PATCH v2 1/4] PCI: Check PCI_PM_CTRL in pci_dev_wait() superm1
2024-07-11 15:07 ` Ilpo Järvinen [this message]
2024-07-11 15:10 ` Mario Limonciello
2024-07-10 20:58 ` [PATCH v2 2/4] PCI: Verify functions currently in D3cold have entered D0 superm1
2024-07-11 15:27 ` Ilpo Järvinen
2024-07-10 20:58 ` [PATCH v2 3/4] PCI: Allow Ryzen XHCI controllers into D3cold and drop delays superm1
2024-07-10 20:58 ` [PATCH v2 4/4] PCI: Drop Radeon quirk for Macbook Pro 8.2 superm1
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