Re: PCIe resets/restore and lack of CRS wait

[Benjamin Herrenschmidt <benh@kernel.crashing.org>]

On Thu, 2018-03-22 at 07:25 -0400, okaya@codeaurora.org wrote:
> > > > 
> > 
> > That tells me that there is no guarantee by spec that we'll get
> > ffff's, instead we might get HW stalls, or other really nasty
> > effects when probing a register other than 0 (VID/DID) for CRS.
> 
> AFAIK, spec also mentions that sw needs to observe 0xffffffff for all 
> other registers other than vendor id during CRS period.

This isnt what's in the 3.1a spec at least ... section 2.3.2 explains
the specified behaviour which is, for any register other than 0
(VID/DID), to re-issue the request...

Now, it can have a timeout, and thus might be completed as a failed
transaction after a while, but it's a sub-optimal way (ie, we'll end up
hogging the CPU on loads) and it's not 100% clear that a failed
transaction returns as all 1's (it should but ...).

I can make sure it happens the way the code expects on powerpc, I'm not
too worried about that, but I think for such a generic function, it
would make sense to stick a bit closer to the spec.

Cheers,
Ben.