[PATCH 0/5] Add MSI-X support for cadence EP driver

[Alan Douglas <adouglas@cadence.com>]

Patch series made against Bjorn Helgaas's pci next branch.
It relies on Gustavo Pimentel's patch series adding MSI-X
support in the PCIe EP driver framework, and implements
MSI-X support for the cadence endpoint driver.
 - Use AXI region 0 for interrupt signalling
 - Write MSI and MSI-X with 32bit value rather than 16bit
 - Check for masking before sending MSI or MSI-X
 - Check link is up before sending IRQ
 - Use BAR5 for MSI-X vectors

Alan Douglas (5):
  PCI: cadence: Use AXI region 0 to signal interrupts from EP
  PCI: cadence: Write MSI data with 32bits
  PCI: cadence: Check whether MSI is masked before sending it
  PCI: cadence: Check link is up before sending IRQ from EP
  PCI: cadence: Add MSI-X capability to EP driver

 drivers/pci/controller/pcie-cadence-ep.c |  129 ++++++++++++++++++++++++++++--
 drivers/pci/controller/pcie-cadence.h    |    1 +
 2 files changed, 124 insertions(+), 6 deletions(-)