From: Alan Douglas <adouglas@cadence.com>
To: <lorenzo.pieralisi@arm.com>
Cc: <kishon@ti.com>, <bhelgaas@google.com>,
<linux-pci@vger.kernel.org>, <gustavo.pimentel@synopsys.com>,
<cyrille.pitchen@bootlin.com>,
Alan Douglas <adouglas@cadence.com>
Subject: [PATCH v4 4/4] PCI: cadence: Check link is up before sending IRQ from EP
Date: Thu, 11 Oct 2018 17:16:57 +0100 [thread overview]
Message-ID: <1539274617-1661-1-git-send-email-adouglas@cadence.com> (raw)
If EP attempts to send an IRQ (legacy, MSI or MSI-X) while the
link is not up, return -EINVAL
Fixes: 37dddf14f1ae ("PCI: cadence: Add EndPoint Controller driver for Cadence PCIe controller")
Signed-off-by: Alan Douglas <adouglas@cadence.com>
---
drivers/pci/controller/pcie-cadence-ep.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
index b762214..3667d70 100644
--- a/drivers/pci/controller/pcie-cadence-ep.c
+++ b/drivers/pci/controller/pcie-cadence-ep.c
@@ -370,6 +370,12 @@ static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
u16 interrupt_num)
{
struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+ u32 link_status;
+
+ /* Can't send an IRQ if the link is down. */
+ link_status = cdns_pcie_readl(&ep->pcie, CDNS_PCIE_LM_BASE);
+ if (!(link_status & 0x1))
+ return -EINVAL;
switch (type) {
case PCI_EPC_IRQ_LEGACY:
--
1.9.0
next reply other threads:[~2018-10-11 16:17 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-11 16:16 Alan Douglas [this message]
2018-10-15 21:30 ` [PATCH v4 4/4] PCI: cadence: Check link is up before sending IRQ from EP Bjorn Helgaas
2018-10-16 13:53 ` Lorenzo Pieralisi
2018-10-16 14:01 ` Alan Douglas
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