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From: Andrei Danaila <adanaila@ctrlinux.com>
To: linux-pci@vger.kernel.org
Subject: Sharing PCIe MMIO with other Drivers
Date: Fri, 09 Nov 2018 16:22:14 -0800	[thread overview]
Message-ID: <1541809334.2290928.1571950584.2632F1FD@webmail.messagingengine.com> (raw)

Hello,

I have a question about best practices in writing an PCIe driver for an FPGA. If this is not the best place to ask, please let me know.

I have an FPGA which is connected over PCIe to an x86 host. The FPGA has a variety of peripherals on it, I2C, UART, SPI etc. All of these peripherals can be accessed from the host by accessing different offsets from the BAR0 address.

I am running linux kernel 4.14 on the host and have written a PCIe device driver which probes off the device id manufacturer ID of the FPGA.

The device driver calls pci_iomap( to obtain the cookie used to access the BAR. This works fine and via this mechanism I can read/write to the FPGA address space after calling ioremap on the cookie.

What I am trying to do now however is create a I2C platform device representing the I2C bus on the FPGA and add to it, as a resource, the BAR0 address + the I2C offset, to get the host's i2c driver to probe off this new PCI device.

In addition I am also trying to add an IRQ number for the I2C driver to use which is an MSIX mapped interrupt number obtained via pci_irq_vector.

In essence, I am trying to get the x86 host to own this device exposed via io-remapped region in PCI land, and use its driver to manage it.

The problem I am having is that I am getting a EBUSY return code when I try to register the resource to the platform device, after the pci_iomap has taken place.

The resource type is IORESOURCE_SYSTEM_RAM | IORESOURCE_MUXED and the start of the resource is the BAR0 address as returned by pci_iomap + I2C_OFFSET.

In the I2C device driver, I am expecting to do an ioremap on the resource and be able to access it by de-refencing


A couple of questions:

1. Is this the correct software flow for managing multiple devices exposed by a PCIe BAR0 address space?
    If not, what is the correct flow?
    If yes, any ideas on what may be going wrong?

Please feel free to point me to any examples, I have looked around quite a bit but did not manage to find enough detail to let me solve this problem.

Thank you

             reply	other threads:[~2018-11-10  0:22 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-10  0:22 Andrei Danaila [this message]
2018-11-10  0:32 ` Sharing PCIe MMIO with other Drivers Sinan Kaya
2018-11-10  0:43   ` Andrei Danaila
2018-11-10  0:48     ` Sinan Kaya
2018-11-10  0:57       ` Andrei Danaila
2018-11-10  1:02         ` Sinan Kaya
2018-11-12  2:26 ` Oliver O'Halloran

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