From: Andrei Danaila <adanaila@ctrlinux.com>
To: Sinan Kaya <okaya@kernel.org>, linux-pci@vger.kernel.org
Subject: Re: Sharing PCIe MMIO with other Drivers
Date: Fri, 09 Nov 2018 16:57:13 -0800 [thread overview]
Message-ID: <1541811433.2126862.1571973360.5D0EF5E6@webmail.messagingengine.com> (raw)
In-Reply-To: <2209a758-fa3a-ba92-a0f0-4cf2d704c10d@kernel.org>
Unfortunately, I cannot change the IP on the FPGA to add more BARs either, the whole thing is locked down.
On Fri, Nov 9, 2018, at 4:48 PM, Sinan Kaya wrote:
> On 11/9/2018 4:43 PM, Andrei Danaila wrote:
> > Thanks Sinan,
> >
> > I thought of that as well, unfortunately that it is not possible since the FPGA IP block is proprietary from a 3P vendor and lumps everything under one function with no option of adding additional functions.
>
> How about adding multiple BARs and then give each BAR to a children driver?
next prev parent reply other threads:[~2018-11-10 0:57 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-10 0:22 Sharing PCIe MMIO with other Drivers Andrei Danaila
2018-11-10 0:32 ` Sinan Kaya
2018-11-10 0:43 ` Andrei Danaila
2018-11-10 0:48 ` Sinan Kaya
2018-11-10 0:57 ` Andrei Danaila [this message]
2018-11-10 1:02 ` Sinan Kaya
2018-11-12 2:26 ` Oliver O'Halloran
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