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From: Lucas Stach <l.stach@pengutronix.de>
To: Stefan Agner <stefan@agner.ch>,
	jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
	tpiepho@impinj.com
Cc: bhelgaas@google.com, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/3] PCI: dwc: allow to limit registers set length
Date: Tue, 20 Nov 2018 15:35:56 +0100	[thread overview]
Message-ID: <1542724556.2508.14.camel@pengutronix.de> (raw)
In-Reply-To: <20181120132705.6917-1-stefan@agner.ch>

Am Dienstag, den 20.11.2018, 14:27 +0100 schrieb Stefan Agner:
> Add length to the struct dw_pcie and check that the accessors
> dw_pcie_(rd|wr)_own_conf() do not read/write beyond that point.
> 
> Signed-off-by: Stefan Agner <stefan@agner.ch>

FWIW:

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

> ---
>  drivers/pci/controller/dwc/pcie-designware-host.c | 4 ++++
>  drivers/pci/controller/dwc/pcie-designware.h      | 1 +
>  2 files changed, 5 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 29a05759a294..b422538ee0bb 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -29,6 +29,8 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
> >  		return pp->ops->rd_own_conf(pp, where, size, val);
>  
> >  	pci = to_dw_pcie_from_pp(pp);
> > +	if (pci->dbi_length && where + size > pci->dbi_length)
> > +		return PCIBIOS_BAD_REGISTER_NUMBER;
> >  	return dw_pcie_read(pci->dbi_base + where, size, val);
>  }
>  
> @@ -41,6 +43,8 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
> >  		return pp->ops->wr_own_conf(pp, where, size, val);
>  
> >  	pci = to_dw_pcie_from_pp(pp);
> > +	if (pci->dbi_length && where + size > pci->dbi_length)
> > +		return PCIBIOS_BAD_REGISTER_NUMBER;
> >  	return dw_pcie_write(pci->dbi_base + where, size, val);
>  }
>  
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 9f1a5e399b70..5be5f369abf2 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -215,6 +215,7 @@ struct dw_pcie {
> > >  	struct device		*dev;
> > >  	void __iomem		*dbi_base;
> > >  	void __iomem		*dbi_base2;
> > > +	int			dbi_length;
> > >  	u32			num_viewport;
> > >  	u8			iatu_unroll_enabled;
> > >  	struct pcie_port	pp;

  parent reply	other threads:[~2018-11-20 14:36 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-20 13:27 [PATCH v2 1/3] PCI: dwc: allow to limit registers set length Stefan Agner
2018-11-20 13:27 ` [PATCH v2 2/3] PCI: imx6: introduce drvdata Stefan Agner
2018-11-20 14:36   ` Lucas Stach
2018-11-20 13:27 ` [PATCH v2 3/3] PCI: imx6: limit DBI register length Stefan Agner
2018-11-20 14:37   ` Lucas Stach
2018-11-28  0:56   ` Andrey Smirnov
2018-11-28  1:12     ` Fabio Estevam
2018-11-28  1:28       ` Andrey Smirnov
2018-11-28 12:45         ` Stefan Agner
2018-11-20 14:35 ` Lucas Stach [this message]
2018-11-20 15:14 ` [PATCH v2 1/3] PCI: dwc: allow to limit registers set length Lorenzo Pieralisi

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