From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85B8CC4360F for ; Thu, 4 Apr 2019 19:55:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 554BE20855 for ; Thu, 4 Apr 2019 19:55:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="rX7viV9L" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730481AbfDDTzz (ORCPT ); Thu, 4 Apr 2019 15:55:55 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:13844 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728699AbfDDTzz (ORCPT ); Thu, 4 Apr 2019 15:55:55 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 04 Apr 2019 12:55:58 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 04 Apr 2019 12:55:54 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 04 Apr 2019 12:55:54 -0700 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 4 Apr 2019 19:55:54 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 4 Apr 2019 19:55:54 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 04 Apr 2019 12:55:53 -0700 From: Vidya Sagar To: , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH V2 07/16] dt-bindings: PCI: designware: Add binding for CDM register check Date: Fri, 5 Apr 2019 01:24:34 +0530 Message-ID: <1554407683-31580-8-git-send-email-vidyas@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554407683-31580-1-git-send-email-vidyas@nvidia.com> References: <1554407683-31580-1-git-send-email-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1554407758; bh=zgKj+7RIvt9aigwah28Aw8pbxJ2+NnzBF4DeWnh2e+A=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=rX7viV9LmOMoPEIorlJYjCicTP+fU6rJ9MImNxd9W8bn3TGWil0nmzQDVNgk1/rNV 2JENQ+sHyAreooj9/DoXuv39nFyX3GfBLjheXTpAD0TnMOleq4TfYw3xFfbGiLbQi5 o+4Vwe/1DnhTQdBBEJL46Blt7RzLjil8+Fn814pwkgdloawcQw1aap/OnOq2U5Vq8x cAYYWRhoaB5GX7iTZ3PGAPJkWzXIoYjYF1OIqOONC0kaV2/XyufuoC0deHWfFJo6hS jbU6GvTFRkHzgpPRrcpKeMdAwzJu5prqsmie/5IenYgidkJjsl9JXja8MUcCVzaWZk u+8gHaQ924XTg== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support to enable CDM (Configuration Dependent Module) registers check for any data corruption. CDM registers include standard PCIe configuration space registers, Port Logic registers and iATU and DMA registers. Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook Version 4.90a Signed-off-by: Vidya Sagar --- Changes since [v1]: * This is a new patch in v2 series Documentation/devicetree/bindings/pci/designware-pcie.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index c124f9bc11f3..728281b5bcd5 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -31,6 +31,10 @@ Optional properties: - clock-names: Must include the following entries: - "pcie" - "pcie_bus" +- cdm-check: This is a boolean property and if present enables automatic + checking of CDM (Configuration Dependent Module) registers for data + corruption. CDM registers include configuration space registers and iATU + (internal Address Translation Unit) registers. RC mode: - num-viewport: number of view ports configured in hardware. If a platform does not specify it, the driver assumes 2. -- 2.7.4