From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qk1-f178.google.com (mail-qk1-f178.google.com [209.85.222.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1391E241671; Mon, 30 Jun 2025 22:25:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.222.178 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751322323; cv=none; b=j73eW6YK9Xf0hX/kvzNGVM0vBF72MhtbynX4tKazEar2U2L3+PVVDdR7vgDlS6hSGj2pZtU04I5+yAd6ys0zzGCacOBTskWMQuAKK0qmPWKa8adHEAYY9Ey7AVwxvDszjCjVDjJLqSEixt0shX6eKFvfuTzZAjY7k5/LeiJC5Ns= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751322323; c=relaxed/simple; bh=9cifePYFORyZXvU9WP3F5RFx+O1sVrMcujhTklc9lOM=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=aCUgItqRXRAuD235YAw4FEg821c/iUVJksn0n21sFhyUFQCYFuoFjtJxXjBVRm75Etmx+IY3T/b55qJd/NuF1SEDilMKVsLBU0E1nCde981j6QgsBm7Z5QQLIudAhz2hYiyvBU72G6/nnC8NyJBQXaf6W5iza6n3x78NoaeNvTQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ipxm7Qxe; arc=none smtp.client-ip=209.85.222.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ipxm7Qxe" Received: by mail-qk1-f178.google.com with SMTP id af79cd13be357-7d3f5796755so467395885a.1; Mon, 30 Jun 2025 15:25:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1751322321; x=1751927121; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=BB+BO3+Ju9SCf7b/TLt6zXjibbwRGCyTQVjEHxQIl60=; b=ipxm7Qxeiq01HAu4Q6bPOy6395K916CkVkLLrmnDX1kdKz3kqQll9B6fdlzU5f5G27 r10DoTf7H0mMZz0FsqTQlg3v4WS15TWLWBw+k05tILbwCcwlVBJsZHPsvfJ6fX1XQn8i Ifk3LpLNwPL5NV1/ziHbhaUN65fwy8BFPIa8lsKCFE6mtO0DwQMSATrjeIbAbNCptvcj 6FQiGWc0/y10STQ06EILCQPhzcsl3M62i/ez7yWD1ov5ZRFG9a84Al8vSrKpUEhHO63k syfvLxSgBiQb4bSInQKBNG2UfUNBJ38rjcwhGyAGSZZzdOwoTnRfsj7HEuYRMEPI8sS3 2jlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751322321; x=1751927121; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=BB+BO3+Ju9SCf7b/TLt6zXjibbwRGCyTQVjEHxQIl60=; b=pdckAzfYNT0RMt+Q+COn3tcRb68slyjx+Gv/Rk41Slorf4ZxLtppECvKr3r9RcC5aN BWvwHzM+7TnyDd1M2QnUZelfRgfJxoz5jVcvLYsEP9Cs6jzVi/R17akenyTZFov3aM+3 j3IDCYx6UKDVb0QkbRADhhNkHnQ3BZNKOFtua0vc7DPE9cube8NkFI+QJm+ua4KCymnS ad0eo585h8TxZEhR+iwqzFOAXRmcjshgopAIXPi0AMRyz8seqsN0eE5DqdCB1dLfEWj0 Lrx6d8mrQFKVgqs1RxNr+2Zb3OUuUyFZQa9b/8Xm6k6ds2+IpKhltC3lgGHvCTdtrOZQ 1gLA== X-Forwarded-Encrypted: i=1; AJvYcCWRLZ/ePci9MNvmq9IgdQB6wDcapurZUQ1FvU8A9hQsjQ6FjV+kl9BGWcmfaqfAnNSd/vckl61FaQnKRDc=@vger.kernel.org, AJvYcCXw0sy6LfuKdy6jIr4tok9JXr/iSo0zpgJIBO3hhzasI9D9C30DP567i1uKIgWrmgZYDlio0PF42/6G@vger.kernel.org X-Gm-Message-State: AOJu0Yxt523/tJw0Qp1ffOGrDsNY3CqxWOH2gc/dLhUNZ+e/2XtcL68j x8/9wKiDHuDUTj4MdAOj/nRez1DYBXzhrVx9JEeeN5EXIcNGUYUKbuNw X-Gm-Gg: ASbGnctn3gl9XYf84EfEoXj4sLigvnNJIhg0sfewbl3RoLSC2dDkio1b12ykp/D2tiB VrkgpYJ90QmMw1MwK5sB/OlpkD5s9EboIDhxLC+VXlp08UxvYoAkDvSqjS7ut/cNb4olG4rKqLN lB9t5JaFb76z8gUmxRjQfFVb0p1F/JGwNzVu+xu/n+HCEVL+WJFAxUhjaVu7x5kJ9pV4ns998EB drovyZNTEWKroPGzW2vEgKK2S13E9WBdhCCu5yN/ZLOnX7lRHxpuRCsmIm0lKllh2svHcOq7P2J jcuBuTdNKtaN+FTgjTUO5KjpNcqIcccfgl63LgeO1LAfMF5Dzg== X-Google-Smtp-Source: AGHT+IFTRrEGCx789ysocz2vuPu09+VjUsb7fSHj7n8oVet+ThKIVJeolTpBlxxkV1sBDbYfdguHzQ== X-Received: by 2002:a05:620a:27c6:b0:7c5:3c0a:ab7e with SMTP id af79cd13be357-7d443909f4amr2207841185a.5.1751322320919; Mon, 30 Jun 2025 15:25:20 -0700 (PDT) Received: from geday ([2804:7f2:800b:4851::dead:c001]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7d44323bba2sm672602885a.109.2025.06.30.15.25.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jun 2025 15:25:20 -0700 (PDT) Date: Mon, 30 Jun 2025 19:25:14 -0300 From: Geraldo Nascimento To: linux-rockchip@lists.infradead.org Cc: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Rick wertenbroek , Neil Armstrong , Valmantas Paliksa , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RESEND PATCH v9 3/4] phy: rockchip-pcie: Enable all four lanes if required Message-ID: <16b610aab34e069fd31d9f57260c10df2a968f80.1751322015.git.geraldogabriel@gmail.com> References: Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: From: Valmantas Paliksa Current code enables only Lane 0 because pwr_cnt will be incremented on first call to the function. Let's reorder the enablement code to enable all 4 lanes through GRF. Reviewed-by: Neil Armstrong Reviewed-by: Robin Murphy Signed-off-by: Valmantas Paliksa Signed-off-by: Geraldo Nascimento --- drivers/phy/rockchip/phy-rockchip-pcie.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c index bd44af36c67a..f22ffb41cdc2 100644 --- a/drivers/phy/rockchip/phy-rockchip-pcie.c +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c @@ -160,6 +160,12 @@ static int rockchip_pcie_phy_power_on(struct phy *phy) guard(mutex)(&rk_phy->pcie_mutex); + regmap_write(rk_phy->reg_base, + rk_phy->phy_data->pcie_laneoff, + HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, + PHY_LANE_IDLE_MASK, + PHY_LANE_IDLE_A_SHIFT + inst->index)); + if (rk_phy->pwr_cnt++) { return 0; } @@ -176,12 +182,6 @@ static int rockchip_pcie_phy_power_on(struct phy *phy) PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT)); - regmap_write(rk_phy->reg_base, - rk_phy->phy_data->pcie_laneoff, - HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, - PHY_LANE_IDLE_MASK, - PHY_LANE_IDLE_A_SHIFT + inst->index)); - /* * No documented timeout value for phy operation below, * so we make it large enough here. And we use loop-break -- 2.49.0