From: "Rob Herring (Arm)" <robh@kernel.org>
To: daire.mcnamara@microchip.com
Cc: linux-kernel@vger.kernel.org, conor.dooley@microchip.com,
kw@linux.com, krzk+dt@kernel.org, devicetree@vger.kernel.org,
lpieralisi@kernel.org, bhelgaas@google.com,
linux-pci@vger.kernel.org, conor+dt@kernel.org,
linux-riscv@lists.infradead.org, ilpo.jarvinen@linux.intel.com
Subject: Re: [PATCH v4 3/3] dt-bindings: PCI: microchip,pcie-host: allow dma-noncoherent
Date: Mon, 24 Jun 2024 13:38:58 -0600 [thread overview]
Message-ID: <171925793172.267714.8378615377109046130.robh@kernel.org> (raw)
In-Reply-To: <20240621112915.3434402-4-daire.mcnamara@microchip.com>
On Fri, 21 Jun 2024 12:29:15 +0100, daire.mcnamara@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> PolarFire SoC may be configured in a way that requires non-coherent DMA
> handling. On RISC-V, buses are coherent by default & the dma-noncoherent
> property is required to denote buses or devices that are non-coherent.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
> ---
> Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
prev parent reply other threads:[~2024-06-24 19:39 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-21 11:29 [PATCH v4 0/3] Fix address translations on MPFS PCIe controller daire.mcnamara
2024-06-21 11:29 ` [PATCH v4 1/3] PCI: microchip: Fix outbound address translation tables daire.mcnamara
2024-06-23 17:02 ` Ilpo Järvinen
2024-06-21 11:29 ` [PATCH v4 2/3] PCI: microchip: Fix inbound " daire.mcnamara
2024-06-23 17:19 ` Ilpo Järvinen
2024-06-21 11:29 ` [PATCH v4 3/3] dt-bindings: PCI: microchip,pcie-host: allow dma-noncoherent daire.mcnamara
2024-06-24 19:38 ` Rob Herring (Arm) [this message]
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