From: Richard Zhu <hongxing.zhu@nxp.com>
To: l.stach@pengutronix.de, kwilczynski@kernel.org,
bhelgaas@google.com, lpieralisi@kernel.org, frank.li@nxp.com,
robh+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org,
krzysztof.kozlowski+dt@linaro.org, festevam@gmail.com,
s.hauer@pengutronix.de
Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
kernel@pengutronix.de, imx@lists.linux.dev,
Richard Zhu <hongxing.zhu@nxp.com>
Subject: [PATCH v1 2/9] PCI: imx6: Add ref clock for i.MX95 PCIe
Date: Tue, 24 Sep 2024 11:27:37 +0800 [thread overview]
Message-ID: <1727148464-14341-3-git-send-email-hongxing.zhu@nxp.com> (raw)
In-Reply-To: <1727148464-14341-1-git-send-email-hongxing.zhu@nxp.com>
Add "ref" clock to enable reference clock.
If use external clock, ref clock should point to external reference.
If use internal clock, CREF_EN in LAST_TO_REG controls reference output,
which implement in drivers/clk/imx/clk-imx95-blk-ctl.c.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 0dbc333adcff..2aa02674c817 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -1480,6 +1480,7 @@ static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"};
static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"};
static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"};
static const char * const imx8q_clks[] = {"mstr", "slv", "dbi"};
+static const char * const imx95_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux", "ref"};
static const struct imx_pcie_drvdata drvdata[] = {
[IMX6Q] = {
@@ -1593,8 +1594,8 @@ static const struct imx_pcie_drvdata drvdata[] = {
[IMX95] = {
.variant = IMX95,
.flags = IMX_PCIE_FLAG_HAS_SERDES,
- .clk_names = imx8mq_clks,
- .clks_cnt = ARRAY_SIZE(imx8mq_clks),
+ .clk_names = imx95_clks,
+ .clks_cnt = ARRAY_SIZE(imx95_clks),
.ltssm_off = IMX95_PE0_GEN_CTRL_3,
.ltssm_mask = IMX95_PCIE_LTSSM_EN,
.mode_off[0] = IMX95_PE0_GEN_CTRL_1,
--
2.37.1
next prev parent reply other threads:[~2024-09-24 3:57 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-24 3:27 [PATCH v1 0/9] A bunch of changes to refine i.MX PCIe driver Richard Zhu
2024-09-24 3:27 ` [PATCH v1 1/9] dt-bindings: imx6q-pcie: Add ref clock for i.MX95 PCIe Richard Zhu
2024-09-24 10:08 ` Conor Dooley
2024-09-24 15:23 ` Frank Li
2024-09-24 16:04 ` Conor Dooley
2024-09-25 2:31 ` Hongxing Zhu
2024-09-24 3:27 ` Richard Zhu [this message]
2024-09-24 15:30 ` [PATCH v1 2/9] PCI: imx6: " Frank Li
2024-09-24 3:27 ` [PATCH v1 3/9] PCI: imx6: Fetch dbi2 and iATU base addesses from DT Richard Zhu
2024-09-24 3:27 ` [PATCH v1 4/9] PCI: imx6: Correct controller_id generation logic for i.MX7D Richard Zhu
2024-09-24 15:31 ` Frank Li
2024-09-24 16:23 ` Frank Li
2024-09-24 3:27 ` [PATCH v1 5/9] PCI: imx6: Make core reset assertion deassertion symmetric Richard Zhu
2024-09-24 16:23 ` Frank Li
2024-09-24 3:27 ` [PATCH v1 6/9] PCI: imx6: Make *_enable_ref_clk() function symmetric Richard Zhu
2024-09-24 16:24 ` Frank Li
2024-09-24 3:27 ` [PATCH v1 7/9] PCI: imx6: Use dwc common suspend resume method Richard Zhu
2024-09-24 3:27 ` [PATCH v1 8/9] PCI: imx6: Add i.MX8MQ i.MX8Q and i.MX95 PCIe PM support Richard Zhu
2024-09-24 16:26 ` Frank Li
2024-09-24 3:27 ` [PATCH v1 9/9] arm64: dts: imx95: Add ref clock for i.MX95 PCIe Richard Zhu
2024-09-24 16:28 ` Frank Li
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