From: Richard Zhu <hongxing.zhu@nxp.com>
To: l.stach@pengutronix.de, kwilczynski@kernel.org,
bhelgaas@google.com, lpieralisi@kernel.org, frank.li@nxp.com,
robh+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org,
krzysztof.kozlowski+dt@linaro.org, festevam@gmail.com,
s.hauer@pengutronix.de
Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
kernel@pengutronix.de, imx@lists.linux.dev,
Richard Zhu <hongxing.zhu@nxp.com>
Subject: [PATCH v1 3/9] PCI: imx6: Fetch dbi2 and iATU base addesses from DT
Date: Tue, 24 Sep 2024 11:27:38 +0800 [thread overview]
Message-ID: <1727148464-14341-4-git-send-email-hongxing.zhu@nxp.com> (raw)
In-Reply-To: <1727148464-14341-1-git-send-email-hongxing.zhu@nxp.com>
Since dbi2 and atu regs are added for i.MX8M PCIes. Fetch the dbi2 and iATU
base addresses from DT directly, and remove the useless codes.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 20 --------------------
1 file changed, 20 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 2aa02674c817..e8e401729893 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -1113,7 +1113,6 @@ static int imx_add_pcie_ep(struct imx_pcie *imx_pcie,
struct platform_device *pdev)
{
int ret;
- unsigned int pcie_dbi2_offset;
struct dw_pcie_ep *ep;
struct dw_pcie *pci = imx_pcie->pci;
struct dw_pcie_rp *pp = &pci->pp;
@@ -1123,25 +1122,6 @@ static int imx_add_pcie_ep(struct imx_pcie *imx_pcie,
ep = &pci->ep;
ep->ops = &pcie_ep_ops;
- switch (imx_pcie->drvdata->variant) {
- case IMX8MQ_EP:
- case IMX8MM_EP:
- case IMX8MP_EP:
- pcie_dbi2_offset = SZ_1M;
- break;
- default:
- pcie_dbi2_offset = SZ_4K;
- break;
- }
-
- pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset;
-
- /*
- * FIXME: Ideally, dbi2 base address should come from DT. But since only IMX95 is defining
- * "dbi2" in DT, "dbi_base2" is set to NULL here for that platform alone so that the DWC
- * core code can fetch that from DT. But once all platform DTs were fixed, this and the
- * above "dbi_base2" setting should be removed.
- */
if (device_property_match_string(dev, "reg-names", "dbi2") >= 0)
pci->dbi_base2 = NULL;
--
2.37.1
next prev parent reply other threads:[~2024-09-24 3:59 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-24 3:27 [PATCH v1 0/9] A bunch of changes to refine i.MX PCIe driver Richard Zhu
2024-09-24 3:27 ` [PATCH v1 1/9] dt-bindings: imx6q-pcie: Add ref clock for i.MX95 PCIe Richard Zhu
2024-09-24 10:08 ` Conor Dooley
2024-09-24 15:23 ` Frank Li
2024-09-24 16:04 ` Conor Dooley
2024-09-25 2:31 ` Hongxing Zhu
2024-09-24 3:27 ` [PATCH v1 2/9] PCI: imx6: " Richard Zhu
2024-09-24 15:30 ` Frank Li
2024-09-24 3:27 ` Richard Zhu [this message]
2024-09-24 3:27 ` [PATCH v1 4/9] PCI: imx6: Correct controller_id generation logic for i.MX7D Richard Zhu
2024-09-24 15:31 ` Frank Li
2024-09-24 16:23 ` Frank Li
2024-09-24 3:27 ` [PATCH v1 5/9] PCI: imx6: Make core reset assertion deassertion symmetric Richard Zhu
2024-09-24 16:23 ` Frank Li
2024-09-24 3:27 ` [PATCH v1 6/9] PCI: imx6: Make *_enable_ref_clk() function symmetric Richard Zhu
2024-09-24 16:24 ` Frank Li
2024-09-24 3:27 ` [PATCH v1 7/9] PCI: imx6: Use dwc common suspend resume method Richard Zhu
2024-09-24 3:27 ` [PATCH v1 8/9] PCI: imx6: Add i.MX8MQ i.MX8Q and i.MX95 PCIe PM support Richard Zhu
2024-09-24 16:26 ` Frank Li
2024-09-24 3:27 ` [PATCH v1 9/9] arm64: dts: imx95: Add ref clock for i.MX95 PCIe Richard Zhu
2024-09-24 16:28 ` Frank Li
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1727148464-14341-4-git-send-email-hongxing.zhu@nxp.com \
--to=hongxing.zhu@nxp.com \
--cc=bhelgaas@google.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=festevam@gmail.com \
--cc=frank.li@nxp.com \
--cc=imx@lists.linux.dev \
--cc=kernel@pengutronix.de \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kwilczynski@kernel.org \
--cc=l.stach@pengutronix.de \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=robh+dt@kernel.org \
--cc=s.hauer@pengutronix.de \
--cc=shawnguo@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).