From: "Rob Herring (Arm)" <robh@kernel.org>
To: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
Cc: lpieralisi@kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, kwilczynski@kernel.org,
bhelgaas@google.com, conor+dt@kernel.org, andersson@kernel.org,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
mani@kernel.org, krzk+dt@kernel.org
Subject: Re: [PATCH] dt-bindings: PCI: qcom,pcie-x1e80100: Set clocks minItems for the fifth Glymur PCIe Controller
Date: Mon, 22 Sep 2025 14:56:01 -0500 [thread overview]
Message-ID: <175857096123.1104979.8944000757958543283.robh@kernel.org> (raw)
In-Reply-To: <20250919142325.1090059-1-pankaj.patil@oss.qualcomm.com>
On Fri, 19 Sep 2025 19:53:25 +0530, Pankaj Patil wrote:
> From: Qiang Yu <qiang.yu@oss.qualcomm.com>
>
> On the Qualcomm Glymur platform, the fifth PCIe host is compatible with
> the DWC controller present on the X1E80100 platform, but does not have
> cnoc_sf_axi clock. Hence, set minItems of clocks and clock-names to six.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
next prev parent reply other threads:[~2025-09-22 19:56 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-19 14:23 [PATCH] dt-bindings: PCI: qcom,pcie-x1e80100: Set clocks minItems for the fifth Glymur PCIe Controller Pankaj Patil
2025-09-22 19:56 ` Rob Herring (Arm) [this message]
2025-09-26 21:15 ` Bjorn Helgaas
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