From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m32101.qiye.163.com (mail-m32101.qiye.163.com [220.197.32.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 750A22857FC for ; Wed, 22 Oct 2025 11:36:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.101 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761132975; cv=none; b=GvBsStQO/AxUBT7EgU9B/QiYw0l0xWMOokxIT0CrVAa1H2doY57qFBAqVs00Yu+Wfbj5+gXvFE+frc887MmIo2Jn4GjRDm9yY8+r4ftMtqndf1h8hDSlvT4gmXVxWzZ5cLNrBTNlhJLGrB8Ue58BNnE2Ez3gRwtO90UhtpZvbVU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761132975; c=relaxed/simple; bh=Vg7JZ9GkmvvTamO+wDgg7+KuYr9RvfqqmYphg7wNnuE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=bwGPocR0/Ez+eqsRmvvfe+LTe05fXqubOvN6lVfivoQgKVFmr52sF/WPAahOB/tHL3gEpAcuJeF3w4v8thBMWVI/f1WAm9a2vvx6Qm0U4u1Hw5sfdXQLhdeJtJ1h+Z0q5Ufgflb5ab353Bitv4SGN26DCY9RTv9xMUjJQJQHs2M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=LjXa+jJW; arc=none smtp.client-ip=220.197.32.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="LjXa+jJW" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 26cdf4383; Wed, 22 Oct 2025 19:36:02 +0800 (GMT+08:00) From: Shawn Lin To: Heiko Stuebner , Manivannan Sadhasivam , Bjorn Helgaas Cc: linux-rockchip@lists.infradead.org, Niklas Cassel , linux-pci@vger.kernel.org, Shawn Lin Subject: [PATCH v2 2/2] arm64: dts: rockchip: Add PCIe clkreq stuff for RK3588 EVB1 Date: Wed, 22 Oct 2025 19:35:54 +0800 Message-Id: <1761132954-177344-2-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1761132954-177344-1-git-send-email-shawn.lin@rock-chips.com> References: <1761132954-177344-1-git-send-email-shawn.lin@rock-chips.com> X-HM-Tid: 0a9a0bb4625509cckunm6eedc7d27fce43 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQ0pCGlZIQ0hCQhhDQklNHU5WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=LjXa+jJWjz3O9NbpU11ts+8LJwBpI29j4jVOOrDg6LI6cNFN8DH7mk5bqTlUU/4rzkpocs2PsiziFEV8kig3fLjgVjiZNNjtQztywYnfUMpPGDp98SiquFjtwV3s8kbV8/VepTKddG29M7qlIQRkgZJ1IEJv/DwZXqik0vM7x5U=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=Yujq5oDMszk1dsRbyLGPp4A3IJYDPlQoxuDFZqCmRio=; h=date:mime-version:subject:message-id:from; Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Add supports-clkreq and pinmux for PCIe ASPM L1 substates. Signed-off-by: Shawn Lin --- Changes in v2: None arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index ff1ba5e..c9d284c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -522,6 +522,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie2_0_rst>, <&pcie2_0_wake>, <&pcie2_0_clkreq>, <&wifi_host_wake_irq>; reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + supports-clkreq; vpcie3v3-supply = <&vcc3v3_wlan>; status = "okay"; @@ -545,7 +546,8 @@ &pcie2x1l1 { reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&pcie2_1_rst>, <&rtl8111_isolate>; + pinctrl-0 = <&pcie2_1_rst>, <&rtl8111_isolate>, <&pcie30x1m1_1_clkreqn>; + supports-clkreq; status = "okay"; }; @@ -555,7 +557,8 @@ &pcie3x4 { pinctrl-names = "default"; - pinctrl-0 = <&pcie3_reset>; + pinctrl-0 = <&pcie3_reset>, <&pcie30x4m1_clkreqn>; + supports-clkreq; reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; status = "okay"; -- 2.7.4