From: Shawn Lin <shawn.lin@rock-chips.com>
To: Manivannan Sadhasivam <mani@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-rockchip@lists.infradead.org, linux-pci@vger.kernel.org,
Shawn Lin <shawn.lin@rock-chips.com>
Subject: [PATCH v2 1/2] PCI: dwc: Add L1 Substates context to ltssm_status of debugfs
Date: Fri, 12 Dec 2025 09:33:24 +0800 [thread overview]
Message-ID: <1765503205-22184-1-git-send-email-shawn.lin@rock-chips.com> (raw)
dwc core couldn't distinguish LTSSM status among L1.0, L1.1 and L1.2.
But the variant driver may implement additional register to tell them
apart. Add two pseudo definitions for variant drivers to translate their
internal L1 Substates for debugfs to show.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
Changes in v2:
- fix the commit log and subject(Bjorn)
- Add space for code comment(Bjorn)
drivers/pci/controller/dwc/pcie-designware-debugfs.c | 2 ++
drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
2 files changed, 6 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers/pci/controller/dwc/pcie-designware-debugfs.c
index 0fbf86c..df98fee 100644
--- a/drivers/pci/controller/dwc/pcie-designware-debugfs.c
+++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c
@@ -485,6 +485,8 @@ static const char *ltssm_status_string(enum dw_pcie_ltssm ltssm)
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ1);
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ2);
DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ3);
+ DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L1_1);
+ DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L1_2);
default:
str = "DW_PCIE_LTSSM_UNKNOWN";
break;
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 3168595..2526664 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -388,6 +388,10 @@ enum dw_pcie_ltssm {
DW_PCIE_LTSSM_RCVRY_EQ2 = 0x22,
DW_PCIE_LTSSM_RCVRY_EQ3 = 0x23,
+ /* Variant drivers provide pseudo L1 substates from get_ltssm() */
+ DW_PCIE_LTSSM_L1_1 = 0x141,
+ DW_PCIE_LTSSM_L1_2 = 0x142,
+
DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF,
};
--
2.7.4
next reply other threads:[~2025-12-12 1:38 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-12 1:33 Shawn Lin [this message]
2025-12-12 1:33 ` [PATCH v2 2/2] PCI: dw-rockchip: Change get_ltssm() to provide L1 Substates info Shawn Lin
2025-12-18 8:25 ` [PATCH v2 1/2] PCI: dwc: Add L1 Substates context to ltssm_status of debugfs Manivannan Sadhasivam
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