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Mon, 22 Dec 2025 09:02:30 -0800 (PST) Received: from [192.168.1.102] ([120.60.139.28]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34e70d4f887sm13636763a91.3.2025.12.22.09.02.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Dec 2025 09:02:30 -0800 (PST) From: Manivannan Sadhasivam X-Google-Original-From: Manivannan Sadhasivam To: Jingoo Han , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Niklas Cassel Cc: Shawn Lin , FUKAUMI Naoki , Krishna chaitanya chundru , Damien Le Moal , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org In-Reply-To: <20251222064207.3246632-8-cassel@kernel.org> References: <20251222064207.3246632-8-cassel@kernel.org> Subject: Re: [PATCH v2 0/6] PCI: dwc: Revert Link Up IRQ support Message-Id: <176642294649.11053.7692165747212741983.b4-ty@kernel.org> Date: Mon, 22 Dec 2025 22:32:26 +0530 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Mailer: b4 0.14.3 X-Authority-Analysis: v=2.4 cv=ELgLElZC c=1 sm=1 tr=0 ts=694979a9 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=wbxd9xFQoh2bOL7BUxlcyw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=875CWLFNMCvb7f9f5gwA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDE1NiBTYWx0ZWRfX223zFTcdrds5 iwqqoeBsQtinu2GXo3CSrGyBSwBg8lcOCFqvwz2kTkTKC5ZaOrCvR1Hm9q74kOWH3VHsrWgVZ6I OZKIC9xEymUagTLh8ZNyBsmld5yVhREggNGbdxjQAaig1qQkN0b6T4z1gjkLgPfmp/u+KveRVu+ 5JW8cQNCBwZh+7UhNBXZfMIrWh3d17BopUcvuvx2aI7NgkTURXdkWtWKO7L9WnDUobYmGmktkA7 PB7bHdZaSv+GcoluDZKnlTzKqC0niLmG6hdNGVg3tM9dHqS/qH368gwlrYBmsiS5rwOHpY6COse +mGeZJiXSHvl1qx+TFViHRtS7Uje0Cuc+2FRvN7HOdyJnbYep9EZdvMfTG9l5yemVQxvadauSpG ywaNk3Rv+crvtD/wdyuAS+HlB2scEoKX1FC4VwGrcD30mmRdMZB91oNhkIrV4T4zJrDtFsHXMsx zdiSF9cNbD++VAip7nQ== X-Proofpoint-GUID: VzRm6RgTL5GdkQ_ypu16dX8RvqdCyh7w X-Proofpoint-ORIG-GUID: VzRm6RgTL5GdkQ_ypu16dX8RvqdCyh7w X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-22_02,2025-12-22_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 spamscore=0 phishscore=0 impostorscore=0 suspectscore=0 adultscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220156 On Mon, 22 Dec 2025 07:42:07 +0100, Niklas Cassel wrote: > Revert all patches related to pcie-designware Root Complex Link Up IRQ > support. > > While this fake hotplugging was a nice idea, it has shown that this feature > does not handle PCIe switches correctly: > pci_bus 0004:43: busn_res: can not insert [bus 43-41] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci_bus 0004:43: busn_res: [bus 43-41] end is updated to 43 > pci_bus 0004:43: busn_res: can not insert [bus 43] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci 0004:42:00.0: devices behind bridge are unusable because [bus 43] cannot be assigned for them > pci_bus 0004:44: busn_res: can not insert [bus 44-41] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci_bus 0004:44: busn_res: [bus 44-41] end is updated to 44 > pci_bus 0004:44: busn_res: can not insert [bus 44] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci 0004:42:02.0: devices behind bridge are unusable because [bus 44] cannot be assigned for them > pci_bus 0004:45: busn_res: can not insert [bus 45-41] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci_bus 0004:45: busn_res: [bus 45-41] end is updated to 45 > pci_bus 0004:45: busn_res: can not insert [bus 45] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci 0004:42:06.0: devices behind bridge are unusable because [bus 45] cannot be assigned for them > pci_bus 0004:46: busn_res: can not insert [bus 46-41] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci_bus 0004:46: busn_res: [bus 46-41] end is updated to 46 > pci_bus 0004:46: busn_res: can not insert [bus 46] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci 0004:42:0e.0: devices behind bridge are unusable because [bus 46] cannot be assigned for them > pci_bus 0004:42: busn_res: [bus 42-41] end is updated to 46 > pci_bus 0004:42: busn_res: can not insert [bus 42-46] under [bus 41] (conflicts with (null) [bus 41]) > pci 0004:41:00.0: devices behind bridge are unusable because [bus 42-46] cannot be assigned for them > pcieport 0004:40:00.0: bridge has subordinate 41 but max busn 46 > > [...] Applied, thanks! [1/6] Revert "PCI: dw-rockchip: Don't wait for link since we can detect Link Up" commit: fc6298086bfacaa7003b0bd1da4e4f42b29f7d77 [2/6] Revert "PCI: dw-rockchip: Enumerate endpoints based on dll_link_up IRQ" commit: 180c3cfe36786d261a55da52a161f9e279b19a6f [3/6] Revert "PCI: qcom: Don't wait for link if we can detect Link Up" commit: e9ce5b3804436301ab343bc14203a4c14b336d1b [4/6] Revert "PCI: qcom: Enable MSI interrupts together with Link up if 'Global IRQ' is supported" commit: 7ebdefb87942073679e56cfbc5a72e8fc5441bfc [5/6] Revert "PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt" commit: 9a9793b55854422652ea92625e48277c4651c0fd [6/6] Revert "PCI: dwc: Don't wait for link up if driver can detect Link Up event" commit: 142d5869f6eec3110adda0ad2d931f5b3c22371d Best regards, -- Manivannan Sadhasivam