From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
To: "Jingoo Han" <jingoohan1@gmail.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Niklas Cassel" <cassel@kernel.org>
Cc: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>,
Frank Li <Frank.Li@nxp.com>, Damien Le Moal <dlemoal@kernel.org>,
Koichiro Den <den@valinux.co.jp>,
linux-pci@vger.kernel.org
Subject: Re: [PATCH v2] PCI: dwc: ep: Cache MSI outbound iATU mapping
Date: Tue, 23 Dec 2025 16:49:20 +0530 [thread overview]
Message-ID: <176648876048.446431.7990743502761229019.b4-ty@kernel.org> (raw)
In-Reply-To: <20251222110144.3299523-2-cassel@kernel.org>
On Mon, 22 Dec 2025 12:01:44 +0100, Niklas Cassel wrote:
> dw_pcie_ep_raise_msi_irq() currently programs an outbound iATU window
> for the MSI target address on every interrupt and tears it down again
> via dw_pcie_ep_unmap_addr().
>
> On systems that heavily use the AXI bridge interface (for example when
> the integrated eDMA engine is active), this means the outbound iATU
> registers are updated while traffic is in flight. The DesignWare
> endpoint databook 5.40a - "3.10.6.1 iATU Outbound Programming Overview"
> warns that updating iATU registers in this situation is not supported,
> and the behavior is undefined.
>
> [...]
Applied, thanks!
[1/1] PCI: dwc: ep: Cache MSI outbound iATU mapping
commit: 8719c64e76bf258cc8f44109740c854f2e2ead2e
Best regards,
--
Manivannan Sadhasivam <mani@kernel.org>
prev parent reply other threads:[~2025-12-23 11:19 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-22 11:01 [PATCH v2] PCI: dwc: ep: Cache MSI outbound iATU mapping Niklas Cassel
2025-12-23 11:19 ` Manivannan Sadhasivam [this message]
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