From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m155106.qiye.163.com (mail-m155106.qiye.163.com [101.71.155.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50CB1330B3E for ; Wed, 24 Dec 2025 10:06:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=101.71.155.106 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766570792; cv=none; b=JQl5aclklOyz2LHhox3RAFcU/IC7TR1V1JydaiifWJz5950+6R8uctXzLyIsNa0o2BQGeiekIr0RZtfRSOs2qX5VvqWFdFJib2XaRljXm+dbmuHH68WuzXhjNh/Ckc+H3ton4575pV9irYqZI/m18sHUuUDN9E2hVAsqi03+HE4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766570792; c=relaxed/simple; bh=ApeN29qgwg0pWjlQfDGpv/UZrZR6jqTxtfsBV2jguAM=; h=From:To:Cc:Subject:Date:Message-Id; b=PHZw8SiEYwgfN5QA75DCaDHQt/a9BePk66eeW+8rQnSVja8UZVNqUnD/AE4dS5WccJLo5sds6mGBZemy8kpTKjpKUFaOoiwOnr6LbEZzJtmgZ1tD1pjls04hleX2+xeOLRkx9OsV7vZx3yf7Z2pwmZG8n39ga+9JKdMH6X8MKmM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=R5uSlLo7; arc=none smtp.client-ip=101.71.155.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="R5uSlLo7" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 2e6ab1f19; Wed, 24 Dec 2025 18:01:09 +0800 (GMT+08:00) From: Shawn Lin To: Manivannan Sadhasivam , Jingoo Han , Bjorn Helgaas Cc: linux-rockchip@lists.infradead.org, Niklas Cassel , linux-pci@vger.kernel.org, Shawn Lin Subject: [PATCH] PCI: dw-rockchip: Disable BAR 0 and BAR 1 for RC mode Date: Wed, 24 Dec 2025 18:01:01 +0800 Message-Id: <1766570461-138256-1-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 2.7.4 X-HM-Tid: 0a9b4fce266e09cckunm298113b63e6deb X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGRlDHVYYTB5CTh9DSkpKGUhWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=R5uSlLo7bMODDKI359E3dWoqT+7y4ciKWlllh+fSLdV0NNq5aVTYhCf2M5ZjF29CDjvzkYeFQ4vhrwO8m5i7UFNN4IJE9FwCZiorKoJ04tHldq0M5wMlQ21xt7SCEy8/hEeqN+NQ+eq2vaJrfaQettxkhndJ4KNqusB4klR4YBg=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=gRw7JySXySjIwbtv2EmWdYL6jpAHHp6rm5lyTwVN6Bo=; h=date:mime-version:subject:message-id:from; Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: To slitence the useless bar allocation error log of RC when scanning bus, as RC doesn't need BARs at all. pci 0000:00:00.0: [1d87:3588] type 01 class 0x060400 PCIe Root Port pci 0000:00:00.0: BAR 0 [mem 0x00000000-0x3fffffff] pci 0000:00:00.0: BAR 1 [mem 0x00000000-0x3fffffff] pci 0000:00:00.0: ROM [mem 0x00000000-0x0000ffff pref] ... pci 0000:00:00.0: BAR 0 [mem 0x900000000-0x93fffffff]: assigned pci 0000:00:00.0: BAR 1 [mem size 0x40000000]: can't assign; no space pci 0000:00:00.0: BAR 1 [mem size 0x40000000]: failed to assign pci 0000:00:00.0: ROM [mem 0xf0200000-0xf020ffff pref]: assigned pci 0000:00:00.0: BAR 0 [mem 0x900000000-0x93fffffff]: releasing pci 0000:00:00.0: ROM [mem 0xf0200000-0xf020ffff pref]: releasing pci 0000:00:00.0: BAR 0 [mem 0x900000000-0x93fffffff]: assigned pci 0000:00:00.0: BAR 1 [mem size 0x40000000]: can't assign; no space pci 0000:00:00.0: BAR 1 [mem size 0x40000000]: failed to assign Signed-off-by: Shawn Lin --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index f8605fe..e421fa0 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -80,6 +80,8 @@ #define PCIE_LINKUP_MASK GENMASK(17, 16) #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) +#define PCIE_TYPE0_HDR_DBI2_OFFSET 0x100000 + struct rockchip_pcie { struct dw_pcie pci; void __iomem *apb_base; @@ -292,6 +294,8 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) if (irq < 0) return irq; + pci->dbi_base2 = pci->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET; + ret = rockchip_pcie_init_irq_domain(rockchip); if (ret < 0) dev_err(dev, "failed to init irq domain\n"); @@ -302,6 +306,10 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) rockchip_pcie_configure_l1ss(pci); rockchip_pcie_enable_l0s(pci); + /* Disable RC's BAR0 and BAR1 */ + dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, 0x0); + dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_1, 0x0); + return 0; } -- 2.7.4