From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
To: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Chen Wang" <unicorn_wang@outlook.com>,
"Inochi Amaoto" <inochiama@gmail.com>
Cc: Han Gao <rabenda.cn@gmail.com>,
linux-pci@vger.kernel.org, sophgo@lists.linux.dev,
linux-kernel@vger.kernel.org, Yixun Lan <dlan@gentoo.org>,
Longbin Li <looong.bin@gmail.com>, Han Gao <gaohan@iscas.ac.cn>
Subject: Re: [PATCH] PCI/sophgo: Avoid L0s and L1 on Sophgo 2044 PCIe Root Ports
Date: Tue, 13 Jan 2026 20:21:44 +0530 [thread overview]
Message-ID: <176831590431.500768.9251307274356703200.b4-ty@kernel.org> (raw)
In-Reply-To: <20260109040756.731169-1-inochiama@gmail.com>
On Fri, 09 Jan 2026 12:07:53 +0800, Inochi Amaoto wrote:
> Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> states for devicetree platforms") force enable ASPM on all device tree
> platform, the SG2044 root port breaks as it advertises L0s and L1
> capabilities without supporting it.
>
> Mask the L0s and L1 Support advertised in Link Capabilities
> in the LINKCAP register SG2044 Root Ports, so the framework
> won't try to enable those states.
>
> [...]
Applied, thanks!
[1/1] PCI/sophgo: Avoid L0s and L1 on Sophgo 2044 PCIe Root Ports
commit: 613f3255a35a95f52575dd8c60b7ac9d711639ce
Best regards,
--
Manivannan Sadhasivam <mani@kernel.org>
prev parent reply other threads:[~2026-01-13 14:51 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-09 4:07 [PATCH] PCI/sophgo: Avoid L0s and L1 on Sophgo 2044 PCIe Root Ports Inochi Amaoto
2026-01-13 14:51 ` Manivannan Sadhasivam [this message]
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