Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport

Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport

[Jingoo Han]

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Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport

[Kishon Vijay Abraham I]

Hi,

On Friday 21 February 2014 07:01 AM, Jingoo Han wrote:
> On Thursday, February 20, 2014 10:34 PM, Mohit KUMAR DCG wrote:
>> Thursday, February 20, 2014 5:43 PM, Kishon Vijay Abraham I wrote:
>>> On Thursday 20 February 2014 05:28 PM, Mohit KUMAR DCG wrote:
>>>> On Thursday, February 20, 2014 5:08 PM, Kishon Vijay Abraham I wrote:
>>>>> On Thursday 20 February 2014 10:52 AM, Mohit Kumar wrote:
>>>>>> This patch correct iATU programming for cfg1, io and mem viewport.
>>>>>> Enable ATU only after configuring it.
>>>>>
>>>>> Does this patch actually fixes device enumeration behind a PCIe-pci
>>>>> bridge or this is more of cleaning up the sequence?
>>>>>
>>>> - This patch corrects ATU programming sequence. I am not aware of any
>>>> such issue with current driver. Pls specify  which bridge do you use in your
>>> setup and what is the problem?
>>>
>>> I tried with card [1], it had a PLX bridge chip. It couldn't read the configuration
>>> space of the device connected to the PCIe-PCI bridge.
>>>
>> - I don’t have the mentioned card with me, but we are successfully using Lecroy PTC switch
>>  and SIL3124-2CB364 PCI-X compatible RAID card.
>>
>> May be Jingoo or others can also comment if they are using PCI bridge card.
>>
> 
> Hi Kishon,
> Nice to see you again. :-)
> 
> I don't have PCIe-PCI bridge. Currently, I can test Ethernet cards
> and SATA cards.

The problem seems to be seen only if a device is connected after PCIe-PCI
bridge. I've tested USB and Ethernet cards but that works just fine.
> 
> By the way, according to the Datasheet, PCIE_ATU_CR1 setting can be
> followed by PCIE_ATU_CR2 setting as below:
> 
>   1. Setup the Index Register.
>   2. Setup the Region Base and Limit Address Registers.
>   3. Setup the Target Address Registers.
>   4. Configure the region through the Region Control 1 Register.
>   5. Enable the region.
> 
> Thus, how about testing the following patch?
> I also moved PCIE_ATU_CR1 as well as PCIE_ATU_CR2.

Thanks for the patch. I have just burnt my PCIE-to-PCI bridge card :-s Will
test this once I get a new card.

Thanks
Kishon

Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport

[Ajay Khandelwal]

Hi Kishon,

On 2/21/2014 10:58 AM, Kishon Vijay Abraham I wrote:
> Thanks for the patch. I have just burnt my PCIE-to-PCI bridge card :-s Will
> test this once I get a new card.

were you able to solve issue in PCIE-to-PCI bridge.

On SPEAr I see issues with PCIe to PCI bridge and PCIe to PCIe switch.

Imprecise external abort is generated, providing hook for abort(similar
to imx6) solves this.

Thanks and Regards,
Ajay

Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport

[Kishon Vijay Abraham I]

On Wednesday 26 February 2014 12:01 PM, Ajay Khandelwal wrote:
> Hi Kishon,
> 
> On 2/21/2014 10:58 AM, Kishon Vijay Abraham I wrote:
>> Thanks for the patch. I have just burnt my PCIE-to-PCI bridge card :-s Will
>> test this once I get a new card.
> 
> were you able to solve issue in PCIE-to-PCI bridge.

oh yes. I was giving the total configuration space as 4k (2k for cfg0 and  2k
for cfg1). But there was some problem when I write 0x800 to
PCIE_ATU_LOWER_BASE. If I read back PCIE_ATU_LOWER_BASE after writing 0x800, it
has 0x0.

So I increased the configuration space to 8k (4k for cfg0 and  4k for cfg1).
With this I write 0x1000 to  PCIE_ATU_LOWER_BASE and able to enumerate devices
behind a PCIE-to-PCI bridge.
> 
> On SPEAr I see issues with PCIe to PCI bridge and PCIe to PCIe switch.
> 
> Imprecise external abort is generated, providing hook for abort(similar
> to imx6) solves this.

But this issue seems to be different :-s

Thanks
Kishon

Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport

[Pratyush Anand]

On Wed, Feb 26, 2014 at 03:47:27PM +0800, Kishon Vijay Abraham I wrote:
> On Wednesday 26 February 2014 12:01 PM, Ajay Khandelwal wrote:
> > Hi Kishon,
> > 
> > On 2/21/2014 10:58 AM, Kishon Vijay Abraham I wrote:
> >> Thanks for the patch. I have just burnt my PCIE-to-PCI bridge card :-s Will
> >> test this once I get a new card.
> > 
> > were you able to solve issue in PCIE-to-PCI bridge.
> 
> oh yes. I was giving the total configuration space as 4k (2k for cfg0 and  2k
> for cfg1). But there was some problem when I write 0x800 to
> PCIE_ATU_LOWER_BASE. If I read back PCIE_ATU_LOWER_BASE after writing 0x800, it
> has 0x0.
> 
> So I increased the configuration space to 8k (4k for cfg0 and  4k for cfg1).
> With this I write 0x1000 to  PCIE_ATU_LOWER_BASE and able to enumerate devices
> behind a PCIE-to-PCI bridge.

As per designware specs minimum value of CX_ATU_MIN_REGION_SIZE is 4 KB.
Depending on the SOC it can be configured from 4 to 64KB. So you can
not have an address translation unit less than 4 KB in any SOC.

I think, it would be worth to mention this information in designware pcie binding
documentation.

However I am surprised, how does it work in case of exynos. Jingoo??
Size of configuration space passed from DT is 0x1000 in exynos. As per
my understanding (and what snps specs says), this value should be
minimum 0x2000 in any SOC, as we divide this space equally for cfg0 and
cfg1 in driver.

Regards
Pratysuh

> > 
> > On SPEAr I see issues with PCIe to PCI bridge and PCIe to PCIe switch.
> > 
> > Imprecise external abort is generated, providing hook for abort(similar
> > to imx6) solves this.
> 
> But this issue seems to be different :-s
> 
> Thanks
> Kishon

Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport

[Jingoo Han]

On Wednesday, February 26, 2014 7:52 PM, Pratyush Anand wrote:
> On Wed, Feb 26, 2014 at 03:47:27PM +0800, Kishon Vijay Abraham I wrote:
> > On Wednesday 26 February 2014 12:01 PM, Ajay Khandelwal wrote:
> > > Hi Kishon,
> > >
> > > On 2/21/2014 10:58 AM, Kishon Vijay Abraham I wrote:
> > >> Thanks for the patch. I have just burnt my PCIE-to-PCI bridge card :-s Will
> > >> test this once I get a new card.
> > >
> > > were you able to solve issue in PCIE-to-PCI bridge.
> >
> > oh yes. I was giving the total configuration space as 4k (2k for cfg0 and  2k
> > for cfg1). But there was some problem when I write 0x800 to
> > PCIE_ATU_LOWER_BASE. If I read back PCIE_ATU_LOWER_BASE after writing 0x800, it
> > has 0x0.
> >
> > So I increased the configuration space to 8k (4k for cfg0 and  4k for cfg1).
> > With this I write 0x1000 to  PCIE_ATU_LOWER_BASE and able to enumerate devices
> > behind a PCIE-to-PCI bridge.
> 
> As per designware specs minimum value of CX_ATU_MIN_REGION_SIZE is 4 KB.
> Depending on the SOC it can be configured from 4 to 64KB. So you can
> not have an address translation unit less than 4 KB in any SOC.

In the case of Exynos, the minimum value of CX_ATU_MIN_REGION_SIZE is 64KB.

> 
> I think, it would be worth to mention this information in designware pcie binding
> documentation.
> 
> However I am surprised, how does it work in case of exynos. Jingoo??

I don't know. However, there was no issue at my side.
Currently, I am testing only Ethernet cards & SATA cards.

> Size of configuration space passed from DT is 0x1000 in exynos. As per
> my understanding (and what snps specs says), this value should be
> minimum 0x2000 in any SOC, as we divide this space equally for cfg0 and
> cfg1 in driver.

I changed 'Size of configuration space passed from DT' from 0x1000 to
0x2000 as below:

	ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00002000   /* configuration space */
		     0x81000000 0 0          0x40002000 0 0x00010000   /* downstream I/O */
   		     0x82000000 0 0x40012000 0x40012000 0 0x1ffee000>; /* non-prefetchable memory */

Then, I tested it on Exynos platform; it works properly with
Ethernet card.

Best regards,
Jingoo Han

> 
> Regards
> Pratysuh
> 
> > >
> > > On SPEAr I see issues with PCIe to PCI bridge and PCIe to PCIe switch.
> > >
> > > Imprecise external abort is generated, providing hook for abort(similar
> > > to imx6) solves this.
> >
> > But this issue seems to be different :-s
> >
> > Thanks
> > Kishon

Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport

[Jingoo Han]

On Thursday, February 27, 2014 10:18 AM, Jingoo Han wrote:
> On Wednesday, February 26, 2014 7:52 PM, Pratyush Anand wrote:
> > On Wed, Feb 26, 2014 at 03:47:27PM +0800, Kishon Vijay Abraham I wrote:
> > > On Wednesday 26 February 2014 12:01 PM, Ajay Khandelwal wrote:
> > > > Hi Kishon,
> > > >
> > > > On 2/21/2014 10:58 AM, Kishon Vijay Abraham I wrote:
> > > >> Thanks for the patch. I have just burnt my PCIE-to-PCI bridge card :-s Will
> > > >> test this once I get a new card.
> > > >
> > > > were you able to solve issue in PCIE-to-PCI bridge.
> > >
> > > oh yes. I was giving the total configuration space as 4k (2k for cfg0 and  2k
> > > for cfg1). But there was some problem when I write 0x800 to
> > > PCIE_ATU_LOWER_BASE. If I read back PCIE_ATU_LOWER_BASE after writing 0x800, it
> > > has 0x0.
> > >
> > > So I increased the configuration space to 8k (4k for cfg0 and  4k for cfg1).
> > > With this I write 0x1000 to  PCIE_ATU_LOWER_BASE and able to enumerate devices
> > > behind a PCIE-to-PCI bridge.
> >
> > As per designware specs minimum value of CX_ATU_MIN_REGION_SIZE is 4 KB.
> > Depending on the SOC it can be configured from 4 to 64KB. So you can
> > not have an address translation unit less than 4 KB in any SOC.
> 
> In the case of Exynos, the minimum value of CX_ATU_MIN_REGION_SIZE is 64KB.

Oh! Sorry.

I got the response from one of our hardware engineers
about 'CX_ATU_MIN_REGION_SIZE'. The minimum value of
CX_ATU_MIN_REGION_SIZE is 4KB.

Sorry for confusing you. :-(

Best regards,
Jingoo Han

> 
> >
> > I think, it would be worth to mention this information in designware pcie binding
> > documentation.
> >
> > However I am surprised, how does it work in case of exynos. Jingoo??
> 
> I don't know. However, there was no issue at my side.
> Currently, I am testing only Ethernet cards & SATA cards.
> 
> > Size of configuration space passed from DT is 0x1000 in exynos. As per
> > my understanding (and what snps specs says), this value should be
> > minimum 0x2000 in any SOC, as we divide this space equally for cfg0 and
> > cfg1 in driver.
> 
> I changed 'Size of configuration space passed from DT' from 0x1000 to
> 0x2000 as below:
> 
> 	ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00002000   /* configuration space */
> 		     0x81000000 0 0          0x40002000 0 0x00010000   /* downstream I/O */
>    		     0x82000000 0 0x40012000 0x40012000 0 0x1ffee000>; /* non-prefetchable memory */
> 
> Then, I tested it on Exynos platform; it works properly with
> Ethernet card.
> 
> Best regards,
> Jingoo Han
> 
> >
> > Regards
> > Pratysuh
> >
> > > >
> > > > On SPEAr I see issues with PCIe to PCI bridge and PCIe to PCIe switch.
> > > >
> > > > Imprecise external abort is generated, providing hook for abort(similar
> > > > to imx6) solves this.
> > >
> > > But this issue seems to be different :-s
> > >
> > > Thanks
> > > Kishon

Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport

[Pratyush Anand]

On Thu, Feb 27, 2014 at 09:37:05AM +0800, Jingoo Han wrote:
> On Thursday, February 27, 2014 10:18 AM, Jingoo Han wrote:
> > On Wednesday, February 26, 2014 7:52 PM, Pratyush Anand wrote:
> > > On Wed, Feb 26, 2014 at 03:47:27PM +0800, Kishon Vijay Abraham I wrote:
> > > > On Wednesday 26 February 2014 12:01 PM, Ajay Khandelwal wrote:
> > > > > Hi Kishon,
> > > > >
> > > > > On 2/21/2014 10:58 AM, Kishon Vijay Abraham I wrote:
> > > > >> Thanks for the patch. I have just burnt my PCIE-to-PCI bridge card :-s Will
> > > > >> test this once I get a new card.
> > > > >
> > > > > were you able to solve issue in PCIE-to-PCI bridge.
> > > >
> > > > oh yes. I was giving the total configuration space as 4k (2k for cfg0 and  2k
> > > > for cfg1). But there was some problem when I write 0x800 to
> > > > PCIE_ATU_LOWER_BASE. If I read back PCIE_ATU_LOWER_BASE after writing 0x800, it
> > > > has 0x0.
> > > >
> > > > So I increased the configuration space to 8k (4k for cfg0 and  4k for cfg1).
> > > > With this I write 0x1000 to  PCIE_ATU_LOWER_BASE and able to enumerate devices
> > > > behind a PCIE-to-PCI bridge.
> > >
> > > As per designware specs minimum value of CX_ATU_MIN_REGION_SIZE is 4 KB.
> > > Depending on the SOC it can be configured from 4 to 64KB. So you can
> > > not have an address translation unit less than 4 KB in any SOC.
> > 
> > In the case of Exynos, the minimum value of CX_ATU_MIN_REGION_SIZE is 64KB.
> 
> Oh! Sorry.
> 
> I got the response from one of our hardware engineers
> about 'CX_ATU_MIN_REGION_SIZE'. The minimum value of
> CX_ATU_MIN_REGION_SIZE is 4KB.

In case of 4 KB, you should keep configuration space size in DT as
0x2000.

With the current value (0x1000) you will not have any problem in cfg0
transfer, however you will not be able to execute cfg1. To test cfg1
transaction you will need a PICe card having multiple EP below a bridge.

Regards
Pratyush
> 
> Sorry for confusing you. :-(
> 
> Best regards,
> Jingoo Han
> 
> > 
> > >
> > > I think, it would be worth to mention this information in designware pcie binding
> > > documentation.
> > >
> > > However I am surprised, how does it work in case of exynos. Jingoo??
> > 
> > I don't know. However, there was no issue at my side.
> > Currently, I am testing only Ethernet cards & SATA cards.
> > 
> > > Size of configuration space passed from DT is 0x1000 in exynos. As per
> > > my understanding (and what snps specs says), this value should be
> > > minimum 0x2000 in any SOC, as we divide this space equally for cfg0 and
> > > cfg1 in driver.
> > 
> > I changed 'Size of configuration space passed from DT' from 0x1000 to
> > 0x2000 as below:
> > 
> > 	ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00002000   /* configuration space */
> > 		     0x81000000 0 0          0x40002000 0 0x00010000   /* downstream I/O */
> >    		     0x82000000 0 0x40012000 0x40012000 0 0x1ffee000>; /* non-prefetchable memory */
> > 
> > Then, I tested it on Exynos platform; it works properly with
> > Ethernet card.
> > 
> > Best regards,
> > Jingoo Han
> > 
> > >
> > > Regards
> > > Pratysuh
> > >
> > > > >
> > > > > On SPEAr I see issues with PCIe to PCI bridge and PCIe to PCIe switch.
> > > > >
> > > > > Imprecise external abort is generated, providing hook for abort(similar
> > > > > to imx6) solves this.
> > > >
> > > > But this issue seems to be different :-s
> > > >
> > > > Thanks
> > > > Kishon

[PATCH 1/2] PCI:designware:Fix comment for setting number of lanes

[Mohit Kumar]

Corrects comment for setting number of lanes.

Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Bjorn Helgaas <bhelgass@google.com>
Cc: spear-devel@list.st.com
Cc: linux-pci@vger.kernel.org
---
 drivers/pci/host/pcie-designware.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 6d23d8c..391966f 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -766,7 +766,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 	u32 membase;
 	u32 memlimit;
 
-	/* set the number of lines as 4 */
+	/* set the number of lanes */
 	dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
 	val &= ~PORT_LINK_MODE_MASK;
 	switch (pp->lanes) {
-- 
1.7.0.1

[PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport

[Mohit Kumar]

This patch correct iATU programming for cfg1, io and mem viewport.
Enable ATU only after configuring it.

Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Ajay Khandelwal <ajay.khandelwal@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Bjorn Helgaas <bhelgass@google.com>
Cc: spear-devel@list.st.com
Cc: linux-pci@vger.kernel.org
---
 drivers/pci/host/pcie-designware.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 391966f..46f4a19 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -522,13 +522,13 @@ static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
 	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
 			  PCIE_ATU_VIEWPORT);
 	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
-	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 	dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
 	dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
 	dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
 			  PCIE_ATU_LIMIT);
 	dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
 	dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
+	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 }
 
 static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
@@ -537,7 +537,6 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
 	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
 			  PCIE_ATU_VIEWPORT);
 	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
-	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 	dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
 	dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
 	dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
@@ -545,6 +544,7 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
 	dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
 	dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
 			  PCIE_ATU_UPPER_TARGET);
+	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 }
 
 static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
@@ -553,7 +553,6 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
 	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
 			  PCIE_ATU_VIEWPORT);
 	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
-	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 	dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
 	dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
 	dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
@@ -561,6 +560,7 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
 	dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
 	dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
 			  PCIE_ATU_UPPER_TARGET);
+	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 }
 
 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
-- 
1.7.0.1

RE: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport

[Mohit KUMAR DCG]

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Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport

[Kishon Vijay Abraham I]

Hi,

On Thursday 20 February 2014 10:52 AM, Mohit Kumar wrote:
> This patch correct iATU programming for cfg1, io and mem viewport.
> Enable ATU only after configuring it.

Does this patch actually fixes device enumeration behind a PCIe-pci bridge or
this is more of cleaning up the sequence?

Thanks
Kishon

> 
> Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
> Signed-off-by: Ajay Khandelwal <ajay.khandelwal@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>
> Cc: Bjorn Helgaas <bhelgass@google.com>
> Cc: spear-devel@list.st.com
> Cc: linux-pci@vger.kernel.org
> ---
>  drivers/pci/host/pcie-designware.c |    6 +++---
>  1 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 391966f..46f4a19 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -522,13 +522,13 @@ static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
>  	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
>  			  PCIE_ATU_VIEWPORT);
>  	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
> -	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
>  	dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
>  	dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
>  	dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
>  			  PCIE_ATU_LIMIT);
>  	dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
>  	dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
> +	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
>  }
>  
>  static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
> @@ -537,7 +537,6 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
>  	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
>  			  PCIE_ATU_VIEWPORT);
>  	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
> -	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
>  	dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
>  	dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
>  	dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
> @@ -545,6 +544,7 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
>  	dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
>  	dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
>  			  PCIE_ATU_UPPER_TARGET);
> +	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
>  }
>  
>  static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
> @@ -553,7 +553,6 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
>  	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
>  			  PCIE_ATU_VIEWPORT);
>  	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
> -	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
>  	dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
>  	dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
>  	dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
> @@ -561,6 +560,7 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
>  	dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
>  	dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
>  			  PCIE_ATU_UPPER_TARGET);
> +	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
>  }
>  
>  static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
> 

RE: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport

[Mohit KUMAR DCG]

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Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport

[Kishon Vijay Abraham I]

Hi Mohit,

On Thursday 20 February 2014 05:28 PM, Mohit KUMAR DCG wrote:
> Hello Kishon,
> 
>> -----Original Message-----
>> From: Kishon Vijay Abraham I [mailto:kishon@ti.com]
>> Sent: Thursday, February 20, 2014 5:08 PM
>> To: Mohit KUMAR DCG; jg1.han@samsung.com
>> Cc: Ajay KHANDELWAL; Bjorn Helgaas; spear-devel; linux-
>> pci@vger.kernel.org
>> Subject: Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io
>> and mem viewport
>>
>> Hi,
>>
>> On Thursday 20 February 2014 10:52 AM, Mohit Kumar wrote:
>>> This patch correct iATU programming for cfg1, io and mem viewport.
>>> Enable ATU only after configuring it.
>>
>> Does this patch actually fixes device enumeration behind a PCIe-pci bridge or
>> this is more of cleaning up the sequence?
>>
> - This patch corrects ATU programming sequence. I am not aware of any such issue with
> current driver. Pls specify  which bridge do you use in your setup and what is the problem?

I tried with card [1], it had a PLX bridge chip. It couldn't read the
configuration space of the device connected to the PCIe-PCI bridge.

Thanks
Kishon

[1] -> http://ratetorate.in/products/Wiretech-PCIe%252dto%252dPCI-Bridge-Card.

> 
> Regards
> Mohit
> 

RE: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport

[Mohit KUMAR DCG]

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Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport

[Pratyush Anand]

On Thu, Feb 20, 2014 at 08:13:08PM +0800, Kishon Vijay Abraham I wrote:
> Hi Mohit,
> 
> On Thursday 20 February 2014 05:28 PM, Mohit KUMAR DCG wrote:
> > Hello Kishon,
> > 
> >> -----Original Message-----
> >> From: Kishon Vijay Abraham I [mailto:kishon@ti.com]
> >> Sent: Thursday, February 20, 2014 5:08 PM
> >> To: Mohit KUMAR DCG; jg1.han@samsung.com
> >> Cc: Ajay KHANDELWAL; Bjorn Helgaas; spear-devel; linux-
> >> pci@vger.kernel.org
> >> Subject: Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io
> >> and mem viewport
> >>
> >> Hi,
> >>
> >> On Thursday 20 February 2014 10:52 AM, Mohit Kumar wrote:
> >>> This patch correct iATU programming for cfg1, io and mem viewport.
> >>> Enable ATU only after configuring it.
> >>
> >> Does this patch actually fixes device enumeration behind a PCIe-pci bridge or
> >> this is more of cleaning up the sequence?
> >>
> > - This patch corrects ATU programming sequence. I am not aware of any such issue with
> > current driver. Pls specify  which bridge do you use in your setup and what is the problem?
> 
> I tried with card [1], it had a PLX bridge chip. It couldn't read the
> configuration space of the device connected to the PCIe-PCI bridge.

So do you see abort while reading config space of device connected to
the PCIe-PCI bridge?

Do you see "received master abort" bit set in your RC's cfg register
after you try to read?

Regards
Pratyush

> 
> Thanks
> Kishon
> 
> [1] -> http://ratetorate.in/products/Wiretech-PCIe%252dto%252dPCI-Bridge-Card.
> 
> > 
> > Regards
> > Mohit
> > 
>