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Mon, 08 Sep 2025 22:01:13 -0700 (PDT) Received: from [192.168.40.164] ([70.105.235.240]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-725dda254d4sm118146646d6.8.2025.09.08.22.01.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Sep 2025 22:01:12 -0700 (PDT) Message-ID: <17c3072e-0c9e-48da-b236-2fefe8ebc823@redhat.com> Date: Tue, 9 Sep 2025 01:01:11 -0400 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 08/11] PCI: Add the ACS Enhanced Capability definitions Content-Language: en-US To: Jason Gunthorpe , Bjorn Helgaas , iommu@lists.linux.dev, Joerg Roedel , linux-pci@vger.kernel.org, Robin Murphy , Will Deacon Cc: Alex Williamson , Lu Baolu , galshalom@nvidia.com, Joerg Roedel , Kevin Tian , kvm@vger.kernel.org, maorg@nvidia.com, patches@lists.linux.dev, tdave@nvidia.com, Tony Zhu References: <8-v3-8827cc7fc4e0+23f-pcie_switch_groups_jgg@nvidia.com> From: Donald Dutile In-Reply-To: <8-v3-8827cc7fc4e0+23f-pcie_switch_groups_jgg@nvidia.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 9/5/25 2:06 PM, Jason Gunthorpe wrote: > This brings the definitions up to PCI Express revision 5.0: > > * ACS I/O Request Blocking Enable > * ACS DSP Memory Target Access Control > * ACS USP Memory Target Access Control > * ACS Unclaimed Request Redirect > > Support for this entire grouping is advertised by the ACS Enhanced > Capability bit. > > Signed-off-by: Jason Gunthorpe > --- > include/uapi/linux/pci_regs.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index 6095e7d7d4cc48..54621e6e83572e 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -1005,8 +1005,16 @@ > #define PCI_ACS_UF 0x0010 /* Upstream Forwarding */ > #define PCI_ACS_EC 0x0020 /* P2P Egress Control */ > #define PCI_ACS_DT 0x0040 /* Direct Translated P2P */ > +#define PCI_ACS_ENHANCED 0x0080 /* IORB, DSP_MT_xx, USP_MT_XX. Capability only */ > +#define PCI_ACS_EGRESS_CTL_SZ GENMASK(15, 8) /* Egress Control Vector Size */ > #define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */ > #define PCI_ACS_CTRL 0x06 /* ACS Control Register */ > +#define PCI_ACS_IORB 0x0080 /* I/O Request Blocking */ > +#define PCI_ACS_DSP_MT_RB 0x0100 /* DSP Memory Target Access Control Request Blocking */ > +#define PCI_ACS_DSP_MT_RR 0x0200 /* DSP Memory Target Access Control Request Redirect */ > +#define PCI_ACS_USP_MT_RB 0x0400 /* USP Memory Target Access Control Request Blocking */ > +#define PCI_ACS_USP_MT_RR 0x0800 /* USP Memory Target Access Control Request Redirect */ > +#define PCI_ACS_UNCLAIMED_RR 0x1000 /* Unclaimed Request Redirect Control */ > #define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ > > /* Reviewed-by: Donald Dutile