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Tue, 20 Feb 2024 06:26:50 -0600 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 20 Feb 2024 06:26:49 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 20 Feb 2024 06:26:49 -0600 Received: from localhost (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41KCQmMl092870; Tue, 20 Feb 2024 06:26:48 -0600 Date: Tue, 20 Feb 2024 17:56:48 +0530 From: Siddharth Vadapalli To: Manivannan Sadhasivam CC: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Kishon Vijay Abraham I , Serge Semin , , , , , , Subject: Re: [PATCH v2 3/5] PCI: dwc: Pass the eDMA mapping format flag directly from glue drivers Message-ID: <17ef7cf1-62d8-41f8-9e52-3ce972708a72@ti.com> References: <20240216-dw-hdma-v2-0-b42329003f43@linaro.org> <20240216-dw-hdma-v2-3-b42329003f43@linaro.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20240216-dw-hdma-v2-3-b42329003f43@linaro.org> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 On 24/02/16 11:04PM, Manivannan Sadhasivam wrote: > Instead of maintaining a separate capability for glue drivers that cannot > support auto detection of the eDMA mapping format, let's pass the mapping > format directly from them. > > This will simplify the code and also allow adding HDMA support that also > doesn't support auto detection of mapping format. > > Suggested-by: Serge Semin > Signed-off-by: Manivannan Sadhasivam Reviewed-by: Siddharth Vadapalli Regards, Siddharth. > --- > drivers/pci/controller/dwc/pcie-designware.c | 16 +++++++++------- > drivers/pci/controller/dwc/pcie-designware.h | 5 ++--- > drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 +- > 3 files changed, 12 insertions(+), 11 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index d07747b75947..54ecd536756d 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -894,18 +894,20 @@ static int dw_pcie_edma_find_mf(struct dw_pcie *pci) > { > u32 val; > > + /* > + * Bail out finding the mapping format if it is already set by the glue > + * driver. Also ensure that the edma.reg_base is pointing to a valid > + * memory region. > + */ > + if (pci->edma.mf != EDMA_MF_EDMA_LEGACY) > + return pci->edma.reg_base ? 0 : -ENODEV; > + > /* > * Indirect eDMA CSRs access has been completely removed since v5.40a > * thus no space is now reserved for the eDMA channels viewport and > * former DMA CTRL register is no longer fixed to FFs. > - * > - * Note that Renesas R-Car S4-8's PCIe controllers for unknown reason > - * have zeros in the eDMA CTRL register even though the HW-manual > - * explicitly states there must FFs if the unrolled mapping is enabled. > - * For such cases the low-level drivers are supposed to manually > - * activate the unrolled mapping to bypass the auto-detection procedure. > */ > - if (dw_pcie_ver_is_ge(pci, 540A) || dw_pcie_cap_is(pci, EDMA_UNROLL)) > + if (dw_pcie_ver_is_ge(pci, 540A)) > val = 0xFFFFFFFF; > else > val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index 26dae4837462..995805279021 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -51,9 +51,8 @@ > > /* DWC PCIe controller capabilities */ > #define DW_PCIE_CAP_REQ_RES 0 > -#define DW_PCIE_CAP_EDMA_UNROLL 1 > -#define DW_PCIE_CAP_IATU_UNROLL 2 > -#define DW_PCIE_CAP_CDM_CHECK 3 > +#define DW_PCIE_CAP_IATU_UNROLL 1 > +#define DW_PCIE_CAP_CDM_CHECK 2 > > #define dw_pcie_cap_is(_pci, _cap) \ > test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps) > diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c > index e9166619b1f9..3c535ef5ea91 100644 > --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c > +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c > @@ -255,7 +255,7 @@ static struct rcar_gen4_pcie *rcar_gen4_pcie_alloc(struct platform_device *pdev) > rcar->dw.ops = &dw_pcie_ops; > rcar->dw.dev = dev; > rcar->pdev = pdev; > - dw_pcie_cap_set(&rcar->dw, EDMA_UNROLL); > + rcar->dw.edma.mf = EDMA_MF_EDMA_UNROLL; > dw_pcie_cap_set(&rcar->dw, REQ_RES); > platform_set_drvdata(pdev, rcar); > > > -- > 2.25.1 > >