From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27176C4332F for ; Mon, 6 Nov 2023 08:46:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231171AbjKFIq5 (ORCPT ); Mon, 6 Nov 2023 03:46:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230466AbjKFIq4 (ORCPT ); Mon, 6 Nov 2023 03:46:56 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8484C9; Mon, 6 Nov 2023 00:46:53 -0800 (PST) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B3131C433C8; Mon, 6 Nov 2023 08:46:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1699260413; bh=EaE06MUOi4Z9hzm+8bzA2VlC213fJCA/ZHevwrNS3qc=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=jMOAsqINnXt3znOUvi4mL6sl+x+5lSJXYViB8rfO8rEXSimHD/joRpCtkhV2/GKfI XD4Fhw5Q8ey+5T5Ef0baW8japB7kubRw+YZLgmO2qqMCe6omPxnQQQQawADalQihZ+ hC5AEKPIl9HxHOMcDVHXXu5sVLastfgioI9TZl8nCZ8gqmKAGN5jBWl/l9OOS6GKIT ehkQGDGOwst3seD5O+uahvD+kKANrJjatz22IF0EXrqLuH1QKaeb4f7KkEdUAvTGaH 4ct4baQfiPXrDclMYeMUtXKKdj84I+gOgo6U+4VGVlzShYX3lvDyF8sJRw0jnpgrLw pR1uxhi1fZQFQ== Message-ID: <1b66b6bc-2a9a-4caa-b4f5-c88f098475e2@kernel.org> Date: Mon, 6 Nov 2023 09:46:42 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/2] PCI: mediatek-gen3: Add power and reset control feature for downstream component To: AngeloGioacchino Del Regno , Jian Yang , Bjorn Helgaas , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Lorenzo Pieralisi , Matthias Brugger , Rob Herring , Jianjun Wang Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Chuanjia.Liu@mediatek.com, Jieyy.Yang@mediatek.com, Qizhong.Cheng@mediatek.com, Jianguo.Zhang@mediatek.com, Bartosz Golaszewski , Abel Vesa References: <20231106061220.21485-1-jian.yang@mediatek.com> <20231106061220.21485-3-jian.yang@mediatek.com> <74e491ce-24c6-4d7a-a1b3-708857f03887@collabora.com> Content-Language: en-US From: Krzysztof Kozlowski Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 06/11/2023 09:36, AngeloGioacchino Del Regno wrote: > Il 06/11/23 08:53, Krzysztof Kozlowski ha scritto: >> On 06/11/2023 07:12, Jian Yang wrote: >>> From: "jian.yang" >>> >>> Make MediaTek's controller driver capable of controlling power >>> supplies and reset pin of a downstream component in power-on and >>> power-off process. >>> >>> Some downstream components (e.g., a WIFI chip) may need an extra >>> reset other than PERST# and their power supplies, depending on >>> the requirements of platform, may need to controlled by their >>> parent's driver. To meet the requirements described above, I add this >>> feature to MediaTek's PCIe controller driver as an optional feature. >> >> NAK, strong NAK. This should be done in a generic way because nothing >> here is specific to Mediatek. >> >> You just implement power sequencing of devices through quirks specific >> to one controller. >> >> Work with others to provide common solution. >> https://lpc.events/event/17/contributions/1507/ >> > > I agree that working with everyone else by adding pwrseq is a must, but other > other PCIe controllers are doing the exact same as this patch: if the supply > and gpio names are aligned with the others, why shouldn't we let this in and > then convert this driver, along with the others, to the new pwrseq subsystem > when it's ready? Because you already push to the PCI controller bindings new properties which are not properties of the PCI controller. > > That, because I expect the pwrseq to require a bit more time before being > ready to get upstream. > > P.S.: Check Tegra, Broadcom, RockChip DW, IMX6Q-pcie. Every new hack will not make it faster. :( At some point one have to say - enough of hacks, start doing it properly with upstream. Best regards, Krzysztof