From: Sinan Kaya <okaya@kernel.org>
To: adanaila@ctrlinux.com, linux-pci@vger.kernel.org
Subject: Re: Sharing PCIe MMIO with other Drivers
Date: Fri, 9 Nov 2018 17:02:52 -0800 [thread overview]
Message-ID: <1e1534d9-bd1f-98ba-1e33-948d81fc6d30@kernel.org> (raw)
In-Reply-To: <1541811433.2126862.1571973360.5D0EF5E6@webmail.messagingengine.com>
On 11/9/2018 4:57 PM, Andrei Danaila wrote:
> Unfortunately, I cannot change the IP on the FPGA to add more BARs either, the whole thing is locked down.
Not the best hardware.
OK. I am running out of ideas. It doesn't play nice with the driver development
model.
One idea is to have a parent PCI driver to allocate BAR space and have children
platform devices that you create at runtime. You can point to arbitrary address
in the system memory map and an IRQ using the platform devices. Though, it might
have some alignment requirement in order to be able to make MMU mappings.
next prev parent reply other threads:[~2018-11-10 1:02 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-10 0:22 Sharing PCIe MMIO with other Drivers Andrei Danaila
2018-11-10 0:32 ` Sinan Kaya
2018-11-10 0:43 ` Andrei Danaila
2018-11-10 0:48 ` Sinan Kaya
2018-11-10 0:57 ` Andrei Danaila
2018-11-10 1:02 ` Sinan Kaya [this message]
2018-11-12 2:26 ` Oliver O'Halloran
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