From: "Rafael J. Wysocki" <rjw@sisk.pl>
To: huang ying <huang.ying.caritas@gmail.com>
Cc: "Yan, Zheng" <zheng.z.yan@intel.com>,
bhelgaas@google.com, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, linux-pm@vger.kernel.org,
Lin Ming <ming.m.lin@intel.com>, Zhang Rui <rui.zhang@intel.com>,
ACPI Devel Mailing List <linux-acpi@vger.kernel.org>
Subject: Re: [RFC PATCH] PCIe: Add PCIe runtime D3cold support
Date: Wed, 18 Apr 2012 21:52:51 +0200 [thread overview]
Message-ID: <201204182152.51421.rjw@sisk.pl> (raw)
In-Reply-To: <CAC=cRTOTZ5Y-urtKLAbuyu8y1ttpG74u3AE0J0_eLg8_8C0PHA@mail.gmail.com>
On Wednesday, April 18, 2012, huang ying wrote:
> On Wed, Apr 18, 2012 at 4:43 AM, Rafael J. Wysocki <rjw@sisk.pl> wrote:
> > On Tuesday, April 17, 2012, huang ying wrote:
> >> On Tue, Apr 17, 2012 at 10:12 AM, Yan, Zheng <zheng.z.yan@intel.com> wrote:
> >> > On 04/17/2012 01:07 AM, Rafael J. Wysocki wrote:
> >> >
> >> >> BTW, can you please explain to me what the #WAKE signal is and how it is
> >> >> different from PME#?
> >> >
> >> > #WAKE signal is triggered by a pin connected to the root complex or other
> >> > motherboard logic. PME# is triggered by PME message sent to the port.
> >>
> >> PME# is a PCI pin, while WAKE# is a PCI Express pin. In PCI Express,
> >> there is no PME#, PME is delivered between end point device and root
> >> port or root complex event collector via PME message, and the PME
> >> message will trigger IRQ on root port or root complex event collector.
> >> WAKE# is not used for PCI Express D1, D2 and D3hot, it is just used
> >> by D3cold. When remote wakeup detected by end point device, it will
> >> assert WAKE# to notify power controller (implemented via ACPI on some
> >> platform), then power controller will turn on power for main link,
> >> after link goes back to L0, PME message will be sent to root port or
> >> root complex event collector by end point device.
> >
> > OK
> >
> > So do I understand correctly that the WAKE# signal here is the one described
> > in Section 5.3.3.2 Link Wakeup of PCI Express Base spec. 2.0?
> >
> > So what happens is that it triggers a GPE and that GPE has a _Lxx method
> > associated with it, I suppose. Is that correct?
>
> Yes.
So I wonder what that _Lxx method looks like.
Thanks,
Rafael
next prev parent reply other threads:[~2012-04-18 19:52 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-04-13 2:35 [RFC PATCH] PCIe: Add PCIe runtime D3cold support Yan, Zheng
2012-04-13 6:06 ` Alex He
2012-04-13 6:28 ` Yan, Zheng
2012-04-16 8:15 ` huang ying
2012-04-13 19:41 ` Rafael J. Wysocki
2012-04-16 0:48 ` Lin Ming
2012-04-16 16:26 ` Rafael J. Wysocki
2012-04-16 2:23 ` Yan, Zheng
2012-04-16 17:07 ` Rafael J. Wysocki
2012-04-17 2:07 ` huang ying
2012-04-17 20:20 ` Rafael J. Wysocki
2012-04-18 1:19 ` huang ying
2012-04-18 19:51 ` Rafael J. Wysocki
2012-04-17 2:12 ` Yan, Zheng
2012-04-17 5:32 ` huang ying
2012-04-17 20:43 ` Rafael J. Wysocki
2012-04-18 1:22 ` huang ying
2012-04-18 19:52 ` Rafael J. Wysocki [this message]
2012-04-17 20:35 ` Rafael J. Wysocki
2012-04-16 7:49 ` Yan, Zheng
2012-04-16 21:11 ` Rafael J. Wysocki
2012-04-16 8:58 ` huang ying
2012-04-16 21:30 ` Rafael J. Wysocki
2012-04-17 2:02 ` huang ying
2012-04-17 21:03 ` Rafael J. Wysocki
2012-04-18 1:45 ` huang ying
2012-04-18 21:00 ` Rafael J. Wysocki
2012-04-19 2:47 ` huang ying
2012-04-19 12:31 ` Rafael J. Wysocki
2012-04-20 0:48 ` huang ying
2012-04-17 5:13 ` huang ying
2012-04-17 21:10 ` Rafael J. Wysocki
2012-04-18 2:01 ` huang ying
2012-04-18 20:51 ` Rafael J. Wysocki
2012-04-19 2:08 ` huang ying
2012-04-19 12:36 ` Rafael J. Wysocki
2012-04-20 0:53 ` huang ying
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