Re: Does my understanding correct?

[Richard Yang <weiyang@linux.vnet.ibm.com>]

On Fri, Apr 27, 2012 at 08:17:48AM -0600, Bjorn Helgaas wrote:
>On Fri, Apr 27, 2012 at 3:27 AM, Richard Yang
><weiyang@linux.vnet.ibm.com> wrote:
>
>I assume your question relates to the Stratus ftServer topology.  If
>so, the lspci details might clarify things.
>
Yes, my picture is a little bit related to your previous mail.
While my intention is to find out how the physical world is represented
in the kernel.

Below is a typical topology in PCIe spec r3.0.

                          +------------------+
                          |                  |
                          |      RC          |
                          |       Bus#0      |                                     
                          | -------------    |                                     
                          |                  |                                     
                          +-+-----+--------+-+                                     
         00:0.0             |     |        |        00:02.0                 
 +---------+---------+      |     |        |       +------------+-------------+
 |                   +------+     |        +-------|  PCIe 2 PCI Bridge       |
 |   PCIe Endpoint   |            |                |                          |
 +-------------------+            |                |  Bus#2                   |
                                  |                |  --------------          |
                                  |                +-------+---------------+--+
                                  |                        |            |       
                                  |  00:01.0               |02:00.0     |02:01.0
                     +------------+-------------+  +-------+------+ +---+-------+
                     |                          |  |PCI dev       | |PCI dev    |
                     |       Switch             |  |              | |           |
                     |       Bus#1              |  |              | |           |
                     |     ---------------      |  +--------------+ +-----------+
                     |                          |                               
                     +------------------------+-+                               
                        |                       |                                      
                        |                       |                                      
                        | 01:00.0               | 01:01.0                                    
              +---------+-------+      +--------+----------------+                    
              |                 |      |                         |                     
              | PCI Endpoint    |      |  PCIe Endpoint          |                     
              |                 |      |                         |                     
              |                 |      |                         |                     
              +-----------------+      +-------------------------+                     

Do you think the current assignment of bus number and pci_dev is
correct?


>In that system, my understanding is that 03:01.0 is a downstream port,
>not an upstream port.
>
>I think your picture is slightly misleading because PCIe links are not
>buses; they're point-to-point links between two devices.  You've drawn
>#3 and #5 as buses that can have several devices on them, which is not
>really the case.  The link from a downstream port should lead to
>exactly one device.
>
>That's one thing that's strange in the ftServer topology: apparently
>there are *two* devices on bus 03: the 03:00.0 upstream port and the
>03:01.0 downstream port.  I think 03:00.0 is the upstream port of a
>PCIe switch, which is perfectly normal.  My understanding is that
>03:01.0 is another *downstream* port that leads to several more
>devices (USB, NIC, etc).
>
>Bjorn

-- 
Richard Yang
Help you, Help me