From: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
To: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Arnd Bergmann <arnd@arndb.de>,
Bjorn Helgaas <bhelgaas@google.com>,
Grant Likely <grant.likely@secretlab.ca>,
Russell King <linux@arm.linux.org.uk>,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
devicetree-discuss@lists.ozlabs.org,
Lior Amsalem <alior@marvell.com>, Andrew Lunn <andrew@lunn.ch>,
Jason Cooper <jason@lakedaemon.net>,
Maen Suleiman <maen@marvell.com>,
Thierry Reding <thierry.reding@avionic-design.de>,
Gregory Clement <gregory.clement@free-electrons.com>,
Ezequiel Garcia <ezequiel.garcia@free-electrons.com>,
Olof Johansson <olof@lixom.net>,
Tawfik Bayouk <tawfik@marvell.com>,
Mitch Bradley <wmb@firmworks.com>,
Andrew Murray <andrew.murray@arm.com>
Subject: Re: [RFCv1 07/11] irqchip: armada-370-xp: add MSI support to interrupt controller driver
Date: Tue, 26 Mar 2013 15:14:03 -0600 [thread overview]
Message-ID: <20130326211403.GA5198@obsidianresearch.com> (raw)
In-Reply-To: <20130326214613.30fbdddf@skate>
On Tue, Mar 26, 2013 at 09:46:13PM +0100, Thomas Petazzoni wrote:
> To me, the topology of the hardware is really that a single device
> provides two features: the main interrupt controller and the MSI
> interrupt controller. But I will adapt to whatever DT binding you
> propose.
No.. the HW is a single device that provides an interrupt on register
write capability, so it ideally should be a single DT node..
The need to distinguish MSI vs IPI vs other usage is completely a side
effect of how Linux's IRQ and PCI layers are hooked together today.
> > I still wonder if the real solution shouldn't instead be to make the
> > irq domain code MSI aware. For instance, you don't really need a
> > cell to describe an interrupt because the interrupt number is
Some kind of generic way for an irq chip driver to say 'here, I can
provide some MSI interrupts' and then for the PCI layer to say 'irq
layer, find me a driver that can provision a MSI with XXX properties' ?
This need to stack an irq chip under a MSI is not something I think
the kernel has had to support before, so new common code is probably
needed...
The interrupt chip should not need to know what the ultimate consumer
of the interrupt capability will be, it just needs to tell the
consumer 'write D to physical address A and irq I will trigger'.
Jason
next prev parent reply other threads:[~2013-03-26 21:14 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-26 16:52 [RFCv1 00/11] MSI support for Marvell EBU PCIe driver Thomas Petazzoni
2013-03-26 16:52 ` [RFCv1 01/11] arm: mvebu: move L2 cache initialization in init_early() Thomas Petazzoni
2013-03-26 16:53 ` Arnd Bergmann
2013-03-26 17:02 ` Thomas Petazzoni
2013-03-27 1:53 ` Rob Herring
2013-03-26 16:52 ` [RFCv1 02/11] irqchip: move IRQ driver for Armada 370/XP Thomas Petazzoni
2013-03-26 16:54 ` Arnd Bergmann
2013-03-26 16:52 ` [RFCv1 03/11] irqchip: armada-370-xp: move IRQ handler to avoid forward declaration Thomas Petazzoni
2013-03-26 16:52 ` [RFCv1 04/11] irqchip: armada-370-xp: slightly cleanup irq controller driver Thomas Petazzoni
2013-03-26 16:52 ` [RFCv1 05/11] arm: mvebu: do not duplicate the mpic alias Thomas Petazzoni
2013-03-26 16:52 ` [RFCv1 06/11] irqchip: armada-370-xp: use a separate mpic node Thomas Petazzoni
2013-03-26 16:52 ` [RFCv1 07/11] irqchip: armada-370-xp: add MSI support to interrupt controller driver Thomas Petazzoni
2013-03-26 17:07 ` Arnd Bergmann
2013-03-26 17:17 ` Thomas Petazzoni
2013-03-26 18:38 ` Arnd Bergmann
2013-03-26 20:46 ` Thomas Petazzoni
2013-03-26 21:10 ` Arnd Bergmann
2013-03-26 21:37 ` Thomas Petazzoni
2013-03-26 21:53 ` Arnd Bergmann
2013-03-26 21:14 ` Jason Gunthorpe [this message]
2013-03-26 21:41 ` Thomas Petazzoni
2013-03-26 18:02 ` Jason Gunthorpe
2013-03-26 21:16 ` Thomas Petazzoni
2013-03-26 21:31 ` Arnd Bergmann
2013-03-26 21:47 ` Thomas Petazzoni
2013-03-26 21:55 ` Jason Gunthorpe
2013-03-26 22:04 ` Arnd Bergmann
2013-03-26 22:06 ` Thomas Petazzoni
2013-03-26 22:26 ` Jason Gunthorpe
2013-03-26 21:15 ` Arnd Bergmann
2013-03-26 21:42 ` Thomas Petazzoni
2013-03-26 16:52 ` [RFCv1 08/11] PCI: Introduce new MSI chip infrastructure Thomas Petazzoni
2013-04-08 22:28 ` Bjorn Helgaas
2013-04-09 8:11 ` Andrew Murray
2013-04-09 8:22 ` Thierry Reding
2013-04-09 8:25 ` Andrew Murray
2013-04-09 8:18 ` Thierry Reding
2013-03-26 16:52 ` [RFCv1 09/11] pci: mvebu: add MSI support Thomas Petazzoni
2013-03-27 10:07 ` Andrew Murray
2013-04-08 22:29 ` Bjorn Helgaas
2013-05-30 12:15 ` Thierry Reding
2013-05-30 18:13 ` Bjorn Helgaas
2013-03-26 16:52 ` [RFCv1 10/11] arm: mvebu: enable MSI support in DT Thomas Petazzoni
2013-03-26 16:52 ` [RFCv1 11/11] arm: mvebu: enable PCI MSI support in defconfig Thomas Petazzoni
2013-03-26 17:05 ` [RFCv1 00/11] MSI support for Marvell EBU PCIe driver Thomas Petazzoni
2013-03-26 17:18 ` Arnd Bergmann
2013-03-26 17:21 ` Thomas Petazzoni
2013-04-04 9:16 ` Ezequiel Garcia
2013-04-04 9:29 ` Thomas Petazzoni
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