From: Wei Yang <weiyang@linux.vnet.ibm.com>
To: Bjorn Helgaas <bhelgaas@google.com>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
Ram Pai <linuxram@us.ibm.com>,
Gavin Shan <shangw@linux.vnet.ibm.com>
Subject: Re: [PATCH 4/4] PCI: fix the io resource alignment calculation in pbus_size_io()
Date: Wed, 10 Jul 2013 09:34:42 +0800 [thread overview]
Message-ID: <20130710013442.GA6671@weiyang.vnet.ibm.com> (raw)
In-Reply-To: <CAErSpo76aKk_Nq=MuL6Rsf98+fTxXQe=bJ-wQOhosKSDoYC8Ew@mail.gmail.com>
On Tue, Jul 09, 2013 at 11:38:06AM -0600, Bjorn Helgaas wrote:
>On Mon, Jul 8, 2013 at 9:20 PM, Wei Yang <weiyang@linux.vnet.ibm.com> wrote:
>> On Mon, Jul 08, 2013 at 03:15:13PM -0600, Bjorn Helgaas wrote:
>>>On Mon, Jul 1, 2013 at 9:10 AM, Wei Yang <weiyang@linux.vnet.ibm.com> wrote:
>>>> In commit 462d9303 ("PCI: Align P2P windows using pcibios_window_alignment()"),
>>>> it introduce a new method to calculate the window alignment of P2P bridge.
>>>>
>>>> When the io_window_1k is set, the calculation for the io resource alignment
>>>> is different from the original one. In the original logic before 462d9303,
>>>> the alignment is no bigger than 4K even the io_window_1k is set. The logic
>>>> introduced in 462d9303 will limit the alignment to 1k in this case.
>>>>
>>>> This patch fix this issue.
>>>>
>>>> Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
>>>> Reviewed-by: Gavin Shan <shangw@linux.vnet.ibm.com>
>>>> Reviewed-by: Ram Pai <linuxram@us.ibm.com>
>>>> ---
>>>> drivers/pci/setup-bus.c | 4 ++++
>>>> 1 files changed, 4 insertions(+), 0 deletions(-)
>>>>
>>>> diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
>>>> index bd0ce39d..5c60ca0 100644
>>>> --- a/drivers/pci/setup-bus.c
>>>> +++ b/drivers/pci/setup-bus.c
>>>> @@ -755,6 +755,10 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
>>>> return;
>>>>
>>>> io_align = min_align = window_alignment(bus, IORESOURCE_IO);
>>>> + /* Don't exceed 4KiB for windows requesting 1KiB alignment */
>>>> + if (bus->self->io_window_1k && io_align == PCI_P2P_DEFAULT_IO_ALIGN_1K)
>>>> + io_align = PCI_P2P_DEFAULT_IO_ALIGN;
>>>
>>>Please explain why we need this change, with some actual values that
>>>show the problem. We need to know what the problem is, not merely
>>>that the code behaves differently than it did before 462d9303.
>>
>> Yep, sorry for not listing the exact problem value.
>>
>> Assume:
>> 1. pcibios_window_alignment() return 1.
>> 2. window_alignment() return PCI_P2P_DEFAULT_IO_ALIGN_1K.
>> 3. one of the child device has an IO resource with size of 2K.
>>
>> Result comparison:
>>
>> Before 462d9303 After 462d9303
>> min_align 1k 1k
>> |
>> after loop |
>> V
>> min_align 2k 2k
>> |
>> check boundary |
>> V
>> min_align 2k 1k
>>
>> In this case, with 462d9303 the min_align will be set back to 1k even one of
>> the child require 2k alignment.
>>
>>>
>>>It appears to me that this change will break the ability to use 1K
>>>windows. For example, assume a bridge that supports 1K windows.
>>>Assume we're using the default pcibios_window_alignment(). Currently
>>>window_alignment() on the secondary bus returns
>>>PCI_P2P_DEFAULT_IO_ALIGN_1K (0x400, which is 1K), so io_align = 0x400.
>>>
>>>With your change, I think io_align will be bumped back up to 4K in
>>>this case, so we'll lose the ability to allocate a 1K window.
>>
>> After applying the change:
>>
>> Assume:
>> 1. pcibios_window_alignment() return 1.
>> 2. window_alignment() return PCI_P2P_DEFAULT_IO_ALIGN_1K.
>> 3. one of the child device has an IO resource with size of 2K.
>
>What happens if no child has an I/O resource larger than 1K? Can we
>allocate a 1K window with 1K alignment in that case?
>
Yes, it could. The result comparison would look like this.
Since no child has an I/O resource larger than 1k, the min_align will remain
1k after loop. And because io_align(4K) is larger than min_align(1k), the
final min_align would be 1k.
In this case, the code from commit 462d9303 and my patch both works.
Result comparison:
with 462d9303 with this patch
min_align 1k 1k
io_align 1k 4k
|
after loop |
V
min_align 1k 1k
io_align 1k 4k
|
check boundary |
V
min_align 1k 1k
io_align 1k 4k
>> Result comparison:
>>
>> with 462d9303 with this patch
>> min_align 1k 1k
>> io_align 1k 4k
>> |
>> after loop |
>> V
>> min_align 2k 2k
>> io_align 1k 4k
>> |
>> check boundary |
>> V
>> min_align 1k 2k
>> io_align 1k 4k
>>
>> With this patch, in the same case as above, the min_align is 2k after
>> calculation.
>>
>> In my mind, the min_align is the lower bound, io_align is the upper bound. The
>> final result of min_align should be in this range.
>>
>> Is my understanding correct? or I missed something important?
>>
>>>
>>>> list_for_each_entry(dev, &bus->devices, bus_list) {
>>>> int i;
>>>>
>>>> --
>>>> 1.7.5.4
>>>>
>>>> --
>>>> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
>>>> the body of a message to majordomo@vger.kernel.org
>>>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>>--
>>>To unsubscribe from this list: send the line "unsubscribe linux-pci" in
>>>the body of a message to majordomo@vger.kernel.org
>>>More majordomo info at http://vger.kernel.org/majordomo-info.html
>>
>> --
>> Richard Yang
>> Help you, Help me
>>
>--
>To unsubscribe from this list: send the line "unsubscribe linux-pci" in
>the body of a message to majordomo@vger.kernel.org
>More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Richard Yang
Help you, Help me
next prev parent reply other threads:[~2013-07-10 1:34 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-01 15:10 [PATCH 0/4] optimization/fix/cleanup in pci_assign_unassigned_resources Wei Yang
2013-07-01 15:10 ` [PATCH 1/4] PCI: optimize pci_bus_get_depth() by enumerating on pci bus hierachy Wei Yang
2013-07-08 20:46 ` Bjorn Helgaas
2013-07-09 2:38 ` Wei Yang
2013-07-09 19:27 ` Bjorn Helgaas
2013-07-10 1:36 ` Wei Yang
2013-07-01 15:10 ` [PATCH 2/4] PCI: add comment for pbus_size_mem() parameter Wei Yang
2013-07-01 15:10 ` [PATCH 3/4] PCI: trivial cleanup in pbus_size_io() Wei Yang
2013-07-01 15:10 ` [PATCH 4/4] PCI: fix the io resource alignment calculation " Wei Yang
2013-07-08 21:15 ` Bjorn Helgaas
2013-07-09 3:20 ` Wei Yang
2013-07-09 17:38 ` Bjorn Helgaas
2013-07-10 1:34 ` Wei Yang [this message]
2013-07-19 3:10 ` Wei Yang
2013-07-25 21:22 ` Bjorn Helgaas
[not found] ` <20130701231040.GA8174@shangw.(null)>
[not found] ` <20130701231540.GA15263@shangw.(null)>
2013-07-02 1:51 ` [PATCH 0/4] optimization/fix/cleanup in pci_assign_unassigned_resources Wei Yang
2013-07-04 1:15 ` Wei Yang
-- strict thread matches above, loose matches on Subject: below --
2013-08-02 9:31 Wei Yang
2013-08-02 9:31 ` [PATCH 4/4] PCI: fix the io resource alignment calculation in pbus_size_io() Wei Yang
2013-08-02 22:51 ` Bjorn Helgaas
2013-08-05 17:58 ` Bjorn Helgaas
2013-08-05 19:05 ` Yinghai Lu
2013-08-05 19:51 ` Bjorn Helgaas
2013-08-05 20:52 ` Yinghai Lu
2013-08-05 20:59 ` Bjorn Helgaas
2013-08-05 21:09 ` Yinghai Lu
2013-08-05 22:21 ` Bjorn Helgaas
2013-08-06 6:15 ` Wei Yang
2013-08-06 13:39 ` Bjorn Helgaas
2013-08-06 15:34 ` Wei Yang
2013-08-06 17:58 ` Bjorn Helgaas
2013-08-07 2:01 ` Wei Yang
[not found] ` <20130806032227.GA7736@shangw.(null)>
2013-08-06 6:26 ` Wei Yang
2013-08-06 13:42 ` Bjorn Helgaas
[not found] ` <52006bfc.6a5d3c0a.2753.ffffa6b7SMTPIN_ADDED_BROKEN@mx.google.com>
2013-08-06 13:35 ` Bjorn Helgaas
2013-08-06 6:19 ` Wei Yang
2013-08-06 13:44 ` Bjorn Helgaas
2013-08-06 15:47 ` Wei Yang
2013-08-06 18:01 ` Bjorn Helgaas
2013-08-06 20:56 ` Bjorn Helgaas
2013-08-07 2:01 ` Wei Yang
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