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From: Thierry Reding <thierry.reding@gmail.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Jay Agarwal <jagarwal@nvidia.com>,
	"linux@arm.linux.org.uk" <linux@arm.linux.org.uk>,
	"swarren@wwwdotorg.org" <swarren@wwwdotorg.org>,
	"thierry.reding@avionic-design.de"
	<thierry.reding@avionic-design.de>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	Laxman Dewangan <ldewangan@nvidia.com>,
	"olof@lixom.net" <olof@lixom.net>,
	Hiroshi Doyu <hdoyu@nvidia.com>,
	Prashant Gaikwad <pgaikwad@nvidia.com>,
	"mturquette@linaro.org" <mturquette@linaro.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	Juha Tukkinen <jtukkinen@nvidia.com>,
	Krishna Thota <kthota@nvidia.com>
Subject: Re: [PATCH V3 3/4] ARM: dts: tegra: Correct PCIe entry
Date: Wed, 17 Jul 2013 06:56:08 +0200	[thread overview]
Message-ID: <20130717045607.GC11359@mithrandir> (raw)
In-Reply-To: <20130611073048.GR3847@tbergstrom-lnx.Nvidia.com>

[-- Attachment #1: Type: text/plain, Size: 1493 bytes --]

On Tue, Jun 11, 2013 at 10:30:48AM +0300, Peter De Schrijver wrote:
> On Mon, Jun 10, 2013 at 09:55:12PM +0200, Thierry Reding wrote:
> > * PGP Signed by an unknown key
> > 
> > On Wed, Jun 05, 2013 at 12:27:31AM +0530, Jay Agarwal wrote:
> > [...]
> > > @@ -29,7 +29,7 @@
> > >  		ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
> > >  			  0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
> > >  			  0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
> > > -			  0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
> > > +			  0x81000000 0 0          0x02000000 0 0x00100000   /* downstream I/O */
> > >  			  0x82000000 0 0x20000000 0x20000000 0 0x10000000   /* non-prefetchable memory */
> > >  			  0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */
> > 
> > That increases the I/O region size from 64 KiB to 1 MiB. Why is that
> > necessary? I/O operations can only address 64 KiB, so I don't think
> > adding more makes any sense.
> 
> At least PCI allows 32bit I/O addresses. No idea if anyone uses them though.

I just realized that we are constrained to 64 KiB by the implementation
of pci_ioremap_io(), which assumes each mapping is 64 KiB. Not that it
couldn't be changed, but unless there actually is a use-case where more
than 64 KiB are required I don't think we should worry about it.

Thierry

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  reply	other threads:[~2013-07-17  4:56 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-06-04 18:57 [PATCH V3 1/4] ARM: tegra30: clocks: Fix pciex clock registration Jay Agarwal
2013-06-04 18:57 ` [PATCH V3 2/4] ARM: tegra: pcie: Add tegra3 support Jay Agarwal
2013-06-04 19:17   ` Stephen Warren
2013-06-05 14:57     ` Jay Agarwal
2013-06-10 19:50     ` Thierry Reding
2013-06-11  4:43       ` Jay Agarwal
2013-06-11 10:16         ` Thierry Reding
2013-06-11 10:40           ` Jay Agarwal
2013-06-04 18:57 ` [PATCH V3 3/4] ARM: dts: tegra: Correct PCIe entry Jay Agarwal
2013-06-10 19:55   ` Thierry Reding
2013-06-11  4:52     ` Jay Agarwal
2013-06-11  7:30     ` Peter De Schrijver
2013-07-17  4:56       ` Thierry Reding [this message]
2013-06-04 18:57 ` [PATCH V3 4/4] ARM: tegra: pcie: Enable PCIe controller on Cardhu Jay Agarwal
2013-06-04 19:08 ` [PATCH V3 1/4] ARM: tegra30: clocks: Fix pciex clock registration Stephen Warren
2013-06-11 22:17   ` Mike Turquette
2013-06-12  7:11     ` Jay Agarwal

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