Re: VIA chipset with Root Port under a bridge

[Wolfgang Denk <wd@denx.de>]

Dear Shaohua Li,

In message <20130823010652.GA1539@kernel.org> you wrote:
> On Thu, Aug 22, 2013 at 03:49:24PM -0600, Bjorn Helgaas wrote:
> > [replace Shaohua's dead Intel address with @kernel.org address; please
> > reply to this, not the original]
> > 
> > On Thu, Aug 22, 2013 at 3:47 PM, Bjorn Helgaas <bhelgaas@google.com> wrote:
> > > Shaohua, your commit 8e822df700 references a VIA chipset with a Root
> > > Port under a bridge, and that commit adds a special case to disable
> > > ASPM for that situation.
> > >
> > > I know this is pretty old (the commit is from 2009), but do you have
> > > any more details about that system?  A pointer to the original problem
> > > report, lspci output, dmesg output, etc.?
> > >
> > > I'm concerned because other parts of PCI make assumptions about Root
> > > Port topology, e.g., in MPS configuration, and we might need to make
> > > similar changes elsewhere.
> 
> I tried to search this in my mail archive, but no success, sorry. Suppose
> Wolfgang reported it, but I can't remember any more details. Maybe check VIA
> datasheet?

Yes, I reported this.  I think I will find all the details in my mail
archives, but I'm currently on vacation with limited access only.
I'll dig this out when I'm back in September.  Please feel free to
send me a reminder if I should not report back within the next two
weeks.

Sorry for the delay.

Best regards,

Wolfgang Denk

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