[PATCH 1/7] lspci: Label PCIe LnkCap "L0s Exit Latency" as "L0s", not "L0"

[PATCH 1/7] lspci: Label PCIe LnkCap "L0s Exit Latency" as "L0s", not "L0"

[Bjorn Helgaas]

The PCIe Link Capabilities "L0s Exit Latency" is the latency to exit
L0s, not L0, so label it "L0s" instead of "L0".  This matches the
way we label the Device Capabilities "Endpoint L0s Acceptable Latency"
field as "Latency L0s".  This also adds "Exit" to the description to
help distinguish it from the "Acceptable Latency" fields in the
Device Capabilities register.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
 ls-caps.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ls-caps.c b/ls-caps.c
index be19d38..a1a1546 100644
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -753,7 +753,7 @@ static void cap_express_link(struct device *d, int where, int type)
   u16 w;
 
   t = get_conf_long(d, where + PCI_EXP_LNKCAP);
-  printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Latency L0 %s, L1 %s\n",
+  printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Exit Latency L0s %s, L1 %s\n",
 	t >> 24,
 	link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
 	aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),

[PATCH 2/7] lspci: Decode PCIe DevCap "Acceptable Latencies" only for Endpoints

[Bjorn Helgaas]

The PCIe Device Capabilities "Endpoint L0s Acceptable Latency" and
"Endpoint L1 Acceptable Latency" are defined only for Endpoint functions,
so don't display them unless this is an endpoint.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
 ls-caps.c |    7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/ls-caps.c b/ls-caps.c
index a1a1546..347f50a 100644
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -659,11 +659,14 @@ static void cap_express_dev(struct device *d, int where, int type)
   u16 w;
 
   t = get_conf_long(d, where + PCI_EXP_DEVCAP);
-  printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d, Latency L0s %s, L1 %s\n",
+  printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d",
 	128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
-	(1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
+	(1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1);
+  if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END))
+    printf(", Latency L0s %s, L1 %s",
 	latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
 	latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
+  printf("\n");
   printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
       (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))

[PATCH 3/7] lspci: Decode PCIe DevCap/DevCtl FLReset only for Endpoints

[Bjorn Helgaas]

The PCIe Device Capabilities and Control bits related to Function
Level Reset are valid only for Endpoints, so only decode them in
that case.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
 ls-caps.c |   11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/ls-caps.c b/ls-caps.c
index 347f50a..7621010 100644
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -673,11 +673,13 @@ static void cap_express_dev(struct device *d, int where, int type)
     printf(" AttnBtn%c AttnInd%c PwrInd%c",
 	FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
 	FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
-  printf(" RBE%c FLReset%c",
-	FLAG(t, PCI_EXP_DEVCAP_RBE),
+  printf(" RBE%c",
+	FLAG(t, PCI_EXP_DEVCAP_RBE));
+  if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END))
+    printf(" FLReset%c",
 	FLAG(t, PCI_EXP_DEVCAP_FLRESET));
   if (type == PCI_EXP_TYPE_UPSTREAM)
-    printf("SlotPowerLimit %.3fW",
+    printf(" SlotPowerLimit %.3fW",
 	power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
 		    (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
   printf("\n");
@@ -696,7 +698,8 @@ static void cap_express_dev(struct device *d, int where, int type)
 	FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
   if (type == PCI_EXP_TYPE_PCI_BRIDGE || type == PCI_EXP_TYPE_PCIE_BRIDGE)
     printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
-  if (type == PCI_EXP_TYPE_ENDPOINT && (t & PCI_EXP_DEVCAP_FLRESET))
+  if (((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END)) &&
+      (t & PCI_EXP_DEVCAP_FLRESET))
     printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
   printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
 	128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),

[PATCH 4/7] lspci: Clarify "PCIe-to-PCI/PCI-X" desc and Bridge Retry Config Enable

[Bjorn Helgaas]

The PCI_EXP_TYPE_PCI_BRIDGE type is a PCIe to PCI/PCI-X bridge, so be a bit
more complete in the comment and printed device type.  Also, per PCIe spec
r3.0, Table 7-14, the PCIe Device Control "Bridge Configuration Retry
Enable" bit only applies to PCIe-to-PCI/PCI-X bridges; it does not apply to
PCI-to-PCIe bridges.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
 lib/header.h |    4 ++--
 ls-caps.c    |    4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/lib/header.h b/lib/header.h
index 6608003..cb63d40 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -728,8 +728,8 @@
 #define  PCI_EXP_TYPE_ROOT_PORT 0x4	/* Root Port */
 #define  PCI_EXP_TYPE_UPSTREAM	0x5	/* Upstream Port */
 #define  PCI_EXP_TYPE_DOWNSTREAM 0x6	/* Downstream Port */
-#define  PCI_EXP_TYPE_PCI_BRIDGE 0x7	/* PCI/PCI-X Bridge */
-#define  PCI_EXP_TYPE_PCIE_BRIDGE 0x8	/* PCI/PCI-X to PCIE Bridge */
+#define  PCI_EXP_TYPE_PCI_BRIDGE 0x7	/* PCIe to PCI/PCI-X Bridge */
+#define  PCI_EXP_TYPE_PCIE_BRIDGE 0x8	/* PCI/PCI-X to PCIe Bridge */
 #define  PCI_EXP_TYPE_ROOT_INT_EP 0x9	/* Root Complex Integrated Endpoint */
 #define  PCI_EXP_TYPE_ROOT_EC 0xa	/* Root Complex Event Collector */
 #define PCI_EXP_FLAGS_SLOT	0x0100	/* Slot implemented */
diff --git a/ls-caps.c b/ls-caps.c
index 7621010..de0d79e 100644
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -696,7 +696,7 @@ static void cap_express_dev(struct device *d, int where, int type)
 	FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
 	FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
 	FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
-  if (type == PCI_EXP_TYPE_PCI_BRIDGE || type == PCI_EXP_TYPE_PCIE_BRIDGE)
+  if (type == PCI_EXP_TYPE_PCI_BRIDGE)
     printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
   if (((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END)) &&
       (t & PCI_EXP_DEVCAP_FLRESET))
@@ -1105,7 +1105,7 @@ cap_express(struct device *d, int where, int cap)
       printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
       break;
     case PCI_EXP_TYPE_PCI_BRIDGE:
-      printf("PCI/PCI-X Bridge");
+      printf("PCI-Express to PCI/PCI-X Bridge");
       break;
     case PCI_EXP_TYPE_PCIE_BRIDGE:
       printf("PCI/PCI-X to PCI-Express Bridge");

[PATCH 5/7] lspci: Decode PCIe LnkCtl "Read Completion Boundary" for PCIe-to-PCI bridges

[Bjorn Helgaas]

The PCIe spec (r3.0, Table 7-16) says the Read Completion Boundary is valid
for Root Ports, Endpoints, and Bridges.  I only added decoding for PCIe-to-
PCI/PCI-X bridges because the RCB of a Bridge indicates the RCB of the
upstream Root Port, so I don't think it makes sense for PCI-to-PCIe
bridges.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
 ls-caps.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ls-caps.c b/ls-caps.c
index de0d79e..3b554fe 100644
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -774,7 +774,7 @@ static void cap_express_link(struct device *d, int where, int type)
   w = get_conf_word(d, where + PCI_EXP_LNKCTL);
   printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
   if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
-      (type == PCI_EXP_TYPE_LEG_END))
+      (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
     printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
   printf(" Disabled%c Retrain%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
 	FLAG(w, PCI_EXP_LNKCTL_DISABLE),

[PATCH 6/7] lspci: Drop PCIe LnkCtl "Retrain Link" decoding

[Bjorn Helgaas]

Per PCIe spec r3.0, Table 7-16, the Retrain Link bit is writable but
always returns 0 when read, so decoding it gives no useful information.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
 ls-caps.c |    3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/ls-caps.c b/ls-caps.c
index 3b554fe..f192510 100644
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -776,9 +776,8 @@ static void cap_express_link(struct device *d, int where, int type)
   if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
       (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
     printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
-  printf(" Disabled%c Retrain%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
+  printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
 	FLAG(w, PCI_EXP_LNKCTL_DISABLE),
-	FLAG(w, PCI_EXP_LNKCTL_RETRAIN),
 	FLAG(w, PCI_EXP_LNKCTL_CLOCK),
 	FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
 	FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),

[PATCH 7/7] lspci: Decode PCIe LnkSta "Link Training" only for relevant functions

[Bjorn Helgaas]

The PCIe Link Status "Link Training" bit is only valid for functions
at the upstream end of a link, i.e., Root Ports, Downstream Ports, and
PCI-to-PCIe Bridges.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
 ls-caps.c |   10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/ls-caps.c b/ls-caps.c
index f192510..87b1a0d 100644
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -786,11 +786,15 @@ static void cap_express_link(struct device *d, int where, int type)
 	FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
 
   w = get_conf_word(d, where + PCI_EXP_LNKSTA);
-  printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
+  printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c",
 	link_speed(w & PCI_EXP_LNKSTA_SPEED),
 	(w & PCI_EXP_LNKSTA_WIDTH) >> 4,
-	FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
-	FLAG(w, PCI_EXP_LNKSTA_TRAIN),
+	FLAG(w, PCI_EXP_LNKSTA_TR_ERR));
+  if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_DOWNSTREAM) ||
+      (type == PCI_EXP_TYPE_PCIE_BRIDGE))
+    printf(" Train%c",
+	FLAG(w, PCI_EXP_LNKSTA_TRAIN));
+  printf(" SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
 	FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
 	FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
 	FLAG(w, PCI_EXP_LNKSTA_BWMGMT),

Re: [PATCH 1/7] lspci: Label PCIe LnkCap "L0s Exit Latency" as "L0s", not "L0"

[Martin Mares]

Hi!

> The PCIe Link Capabilities "L0s Exit Latency" is the latency to exit
> L0s, not L0, so label it "L0s" instead of "L0".  This matches the
> way we label the Device Capabilities "Endpoint L0s Acceptable Latency"
> field as "Latency L0s".  This also adds "Exit" to the description to
> help distinguish it from the "Acceptable Latency" fields in the
> Device Capabilities register.

Applied the whole patch set.

				Have a nice fortnight
-- 
Martin `MJ' Mares                          <mj@ucw.cz>   http://mj.ucw.cz/
Faculty of Math and Physics, Charles University, Prague, Czech Rep., Earth
To understand a program you must become both the machine and the program.