From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
To: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Jason Cooper <jason@lakedaemon.net>,
Ezequiel Garcia <ezequiel.garcia@free-electrons.com>,
linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH] PCI: mvebu - The bridge secondary status register should be 0
Date: Thu, 31 Oct 2013 09:54:46 +0100 [thread overview]
Message-ID: <20131031095446.3c95fbb5@skate> (raw)
In-Reply-To: <1381868190-8595-1-git-send-email-jgunthorpe@obsidianresearch.com>
Dear Jason Gunthorpe,
On Tue, 15 Oct 2013 14:16:30 -0600, Jason Gunthorpe wrote:
> There are no writable bits in the secondary status register, only
> write 1 to clear bits. The driver never sets any of the write 1 to
> clear bits so the status register should always be 0, just remove
> the set from the write path.
>
> Someday the write 1 to clear bits should be copied/cleared directly
> from registers in the HW.
>
> Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
next prev parent reply other threads:[~2013-10-31 8:54 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-15 20:16 [PATCH] PCI: mvebu - The bridge secondary status register should be 0 Jason Gunthorpe
2013-10-17 13:12 ` Jason Cooper
2013-10-31 8:54 ` Thomas Petazzoni [this message]
-- strict thread matches above, loose matches on Subject: below --
2013-11-26 18:02 Jason Gunthorpe
2013-11-26 18:23 ` Jason Cooper
2013-11-26 18:38 ` Bjorn Helgaas
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