* [PATCH] PCI: mvebu - The bridge secondary status register should be 0
@ 2013-10-15 20:16 Jason Gunthorpe
2013-10-17 13:12 ` Jason Cooper
2013-10-31 8:54 ` Thomas Petazzoni
0 siblings, 2 replies; 6+ messages in thread
From: Jason Gunthorpe @ 2013-10-15 20:16 UTC (permalink / raw)
To: Thomas Petazzoni
Cc: Jason Cooper, Ezequiel Garcia, linux-arm-kernel, linux-pci
There are no writable bits in the secondary status register, only
write 1 to clear bits. The driver never sets any of the write 1 to
clear bits so the status register should always be 0, just remove
the set from the write path.
Someday the write 1 to clear bits should be copied/cleared directly
from registers in the HW.
Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
---
drivers/pci/host/pci-mvebu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index 09fc586..3e5cdbd 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -495,7 +495,6 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
*/
bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
- bridge->secondary_status = value >> 16;
mvebu_pcie_handle_iobase_change(port);
break;
--
1.8.1.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] PCI: mvebu - The bridge secondary status register should be 0
2013-10-15 20:16 [PATCH] PCI: mvebu - The bridge secondary status register should be 0 Jason Gunthorpe
@ 2013-10-17 13:12 ` Jason Cooper
2013-10-31 8:54 ` Thomas Petazzoni
1 sibling, 0 replies; 6+ messages in thread
From: Jason Cooper @ 2013-10-17 13:12 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: Thomas Petazzoni, linux-arm-kernel, linux-pci, Ezequiel Garcia
On Tue, Oct 15, 2013 at 02:16:30PM -0600, Jason Gunthorpe wrote:
> There are no writable bits in the secondary status register, only
> write 1 to clear bits. The driver never sets any of the write 1 to
> clear bits so the status register should always be 0, just remove
> the set from the write path.
>
> Someday the write 1 to clear bits should be copied/cleared directly
> from registers in the HW.
>
> Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
> ---
> drivers/pci/host/pci-mvebu.c | 1 -
> 1 file changed, 1 deletion(-)
Applied to mvebu/drivers
thx,
Jason.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] PCI: mvebu - The bridge secondary status register should be 0
2013-10-15 20:16 [PATCH] PCI: mvebu - The bridge secondary status register should be 0 Jason Gunthorpe
2013-10-17 13:12 ` Jason Cooper
@ 2013-10-31 8:54 ` Thomas Petazzoni
1 sibling, 0 replies; 6+ messages in thread
From: Thomas Petazzoni @ 2013-10-31 8:54 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: Jason Cooper, Ezequiel Garcia, linux-arm-kernel, linux-pci
Dear Jason Gunthorpe,
On Tue, 15 Oct 2013 14:16:30 -0600, Jason Gunthorpe wrote:
> There are no writable bits in the secondary status register, only
> write 1 to clear bits. The driver never sets any of the write 1 to
> clear bits so the status register should always be 0, just remove
> the set from the write path.
>
> Someday the write 1 to clear bits should be copied/cleared directly
> from registers in the HW.
>
> Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] PCI: mvebu - The bridge secondary status register should be 0
@ 2013-11-26 18:02 Jason Gunthorpe
2013-11-26 18:23 ` Jason Cooper
0 siblings, 1 reply; 6+ messages in thread
From: Jason Gunthorpe @ 2013-11-26 18:02 UTC (permalink / raw)
To: Bjorn Helgaas, Jason Cooper, Thomas Petazzoni
Cc: Ezequiel Garcia, linux-arm-kernel, linux-pci
There are no writable bits in the secondary status register, only
write 1 to clear bits. The driver never sets any of the write 1 to
clear bits so the status register should always be 0, just remove
the set from the write path.
Someday the write 1 to clear bits should be copied/cleared directly
from registers in the HW.
Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
---
drivers/pci/host/pci-mvebu.c | 1 -
1 file changed, 1 deletion(-)
Thomas: This was the last patch in my set that you haven't reviewed. Thanks
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index c269e43..6f5a20f 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -500,7 +500,6 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
*/
bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
- bridge->secondary_status = value >> 16;
mvebu_pcie_handle_iobase_change(port);
break;
--
1.8.1.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] PCI: mvebu - The bridge secondary status register should be 0
2013-11-26 18:02 Jason Gunthorpe
@ 2013-11-26 18:23 ` Jason Cooper
2013-11-26 18:38 ` Bjorn Helgaas
0 siblings, 1 reply; 6+ messages in thread
From: Jason Cooper @ 2013-11-26 18:23 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: Bjorn Helgaas, Thomas Petazzoni, Ezequiel Garcia,
linux-arm-kernel, linux-pci
On Tue, Nov 26, 2013 at 11:02:52AM -0700, Jason Gunthorpe wrote:
> There are no writable bits in the secondary status register, only
> write 1 to clear bits. The driver never sets any of the write 1 to
> clear bits so the status register should always be 0, just remove
> the set from the write path.
>
> Someday the write 1 to clear bits should be copied/cleared directly
> from registers in the HW.
>
> Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
> ---
> drivers/pci/host/pci-mvebu.c | 1 -
> 1 file changed, 1 deletion(-)
Whole series
Acked-by: Jason Cooper <jason@lakedaemon.net>
thx,
Jason.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] PCI: mvebu - The bridge secondary status register should be 0
2013-11-26 18:23 ` Jason Cooper
@ 2013-11-26 18:38 ` Bjorn Helgaas
0 siblings, 0 replies; 6+ messages in thread
From: Bjorn Helgaas @ 2013-11-26 18:38 UTC (permalink / raw)
To: Jason Cooper
Cc: Jason Gunthorpe, Thomas Petazzoni, Ezequiel Garcia,
linux-arm-kernel, linux-pci
On Tue, Nov 26, 2013 at 01:23:28PM -0500, Jason Cooper wrote:
> On Tue, Nov 26, 2013 at 11:02:52AM -0700, Jason Gunthorpe wrote:
> > There are no writable bits in the secondary status register, only
> > write 1 to clear bits. The driver never sets any of the write 1 to
> > clear bits so the status register should always be 0, just remove
> > the set from the write path.
> >
> > Someday the write 1 to clear bits should be copied/cleared directly
> > from registers in the HW.
> >
> > Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
> > ---
> > drivers/pci/host/pci-mvebu.c | 1 -
> > 1 file changed, 1 deletion(-)
>
> Whole series
>
> Acked-by: Jason Cooper <jason@lakedaemon.net>
Thanks, I applied the Interrupt Line/Pin change to for-linus for v3.13, and
the others to pci/host-mvebu for v3.14.
Bjorn
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2013-11-26 18:38 UTC | newest]
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2013-10-15 20:16 [PATCH] PCI: mvebu - The bridge secondary status register should be 0 Jason Gunthorpe
2013-10-17 13:12 ` Jason Cooper
2013-10-31 8:54 ` Thomas Petazzoni
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2013-11-26 18:23 ` Jason Cooper
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