From: "Jürgen Beisert" <jbe@pengutronix.de>
To: linux-arm-kernel@lists.infradead.org
Cc: Marek Vasut <marex@denx.de>, linux-pci@vger.kernel.org
Subject: Re: [PATCH 0/6] PCI: imx6: Random fixes
Date: Mon, 11 Nov 2013 14:32:59 +0100 [thread overview]
Message-ID: <201311111432.59318.jbe@pengutronix.de> (raw)
In-Reply-To: <1381853200-5534-1-git-send-email-marex@denx.de>
Hi,
I'm also trying to get the PCIe to work on an i.MX6. But the attached device
cannot be enabled. The external device is an FPGA directly connected to the
i.MX6. I'm using the changes from linux-next to get the machine working up
to this point. But it seems I still miss something.
What I see is:
[...]
PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [io 0x1000-0x10000]
pci_bus 0000:00: root bus resource [mem 0x01000000-0x01efffff]
pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
pci_bus 0000:00: scanning bus
pci 0000:00:00.0: [16c3:abcd] type 01 class 0x060400
pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff]
pci 0000:00:00.0: reg 0x38: [mem 0x00000000-0x0000ffff pref]
pci 0000:00:00.0: calling pci_fixup_ide_bases+0x0/0x5c
pci 0000:00:00.0: supports D1
pci 0000:00:00.0: PME# supported from D0 D1 D3hot D3cold
pci 0000:00:00.0: PME# disabled
pci_bus 0000:00: fixups for bus
PCI: bus0: Fast back to back transfers disabled
pci 0000:00:00.0: scanning [bus 01-01] behind bridge, pass 0
pci 0000:00:00.0: scanning [bus 00-00] behind bridge, pass 1
pci_bus 0000:01: scanning bus
pci 0000:01:00.0: [1172:0004] type 00 class 0x000000
pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x0000ffff]
pci 0000:01:00.0: calling pci_fixup_ide_bases+0x0/0x5c
pci_bus 0000:01: fixups for bus
PCI: bus1: Fast back to back transfers disabled
pci_bus 0000:01: bus scan returning with max=01
pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
pci_bus 0000:00: bus scan returning with max=01
pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 01
pci 0000:00:00.0: fixup irq: got 155
pci 0000:00:00.0: assigning IRQ 155
pci 0000:01:00.0: fixup irq: got 155
pci 0000:01:00.0: assigning IRQ 155
pci 0000:00:00.0: BAR 0: assigned [mem 0x01000000-0x010fffff]
pci 0000:00:00.0: BAR 0: set to [mem 0x01000000-0x010fffff] (PCI address [0x1000000-0x10fffff])
pci 0000:00:00.0: BAR 8: assigned [mem 0x01100000-0x011fffff]
pci 0000:00:00.0: BAR 6: assigned [mem 0x01200000-0x0120ffff pref]
pci 0000:00:00.0: PCI bridge to [bus 01]
pci 0000:00:00.0: bridge window [mem 0x01100000-0x011fffff]
pci_bus 0000:00: max bus depth: 1 pci_try_num: 2
pci 0000:00:00.0: PCI bridge to [bus 01]
pci 0000:00:00.0: bridge window [mem 0x01100000-0x011fffff]
pci_bus 0000:00: resource 4 [io 0x1000-0x10000]
pci_bus 0000:00: resource 5 [mem 0x01000000-0x01efffff]
pci_bus 0000:01: resource 1 [mem 0x01100000-0x011fffff]
[...]
pcieport 0000:00:00.0: Resource 0: from 1000000 to 10FFFFF <- my message from pcibios_enable_device()/arch/arm/kernel/bios32.c
[...]
FPGA 0000:01:00.0: Dummy FPGA driver starts probing
FPGA 0000:01:00.0: Resource 0: from 0 to FFFF <- my message from pcibios_enable_device()/arch/arm/kernel/bios32.c
PCI: Device 0000:01:00.0 not available because of resource collisions
FPGA 000:01:00.0: Cannot enable PCIe device, aborting
FPGA: probe of 0000:01:00.0 failed with error -5
pcibios_enable_device() fails due to the start address of this device is
still 0.
Accesses to the configuration space are working. Here the output:
root@platform:~ lspci -vv
00:00.0 PCI bridge: Device 16c3:abcd (rev 01) (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Region 0: Memory at 01000000 (32-bit, non-prefetchable) [size=1M]
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
Memory behind bridge: 01100000-011fffff
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
[virtual] Expansion ROM at 01200000 [disabled] [size=64K]
BridgeCtl: Parity+ SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [50] MSI: Mask+ 64bit+ Count=1/1 Enable+
Address: 0000000090000000 Data: 0000
Masking: 00000001 Pending: 00000000
Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
ExtTag- RBE+ FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 unlimited
ClockPM- Surprise- LLActRep+ BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd-
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd-
LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -6dB
Capabilities: [100] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
Capabilities: [140] Virtual Channel <?>
Kernel driver in use: pcieport
01:00.0 Non-VGA unclassified device: Altera Corporation Device 0004 (rev 01)
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Interrupt: pin A routed to IRQ 155
Capabilities: [50] MSI: Mask- 64bit+ Count=1/1 Enable-
Address: 0000000000000000 Data: 0000
Capabilities: [78] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [80] Express (v2) Endpoint, MSI 00
DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
LnkCap: Port #1, Speed 5GT/s, Width x1, ASPM unknown, Latency L0 <4us, L1 <1us
ClockPM- Surprise- LLActRep- BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-
LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -6dB
Capabilities: [100] Virtual Channel <?>
Capabilities: [200] Vendor Specific Information <?>
Any idea what is missing?
Regards,
Juergen
--
Pengutronix e.K. | Juergen Beisert |
Linux Solutions for Science and Industry | http://www.pengutronix.de/ |
next prev parent reply other threads:[~2013-11-11 13:31 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-15 16:06 [PATCH 0/6] PCI: imx6: Random fixes Marek Vasut
2013-10-15 16:06 ` [PATCH 1/6] PCI: imx6: Make reset-gpio optional Marek Vasut
2013-10-16 1:24 ` Jingoo Han
2013-10-15 16:06 ` [PATCH 2/6] PCI: imx6: Fix the clock for PCIe Marek Vasut
2013-10-15 16:06 ` [PATCH 3/6] ARM: dts: imx6qdl: " Marek Vasut
2013-10-15 16:06 ` [PATCH 4/6] PCI: imx6: Probe the PCIe in fs_initcall() Marek Vasut
2013-10-17 23:31 ` Tim Harvey
2013-10-15 16:06 ` [PATCH 5/6] PCI: imx6: Force Gen1 operation Marek Vasut
2013-10-16 5:54 ` Pratyush Anand
2013-10-16 13:57 ` Marek Vasut
2013-10-17 7:02 ` Zhu Richard-R65037
2013-10-17 17:34 ` Marek Vasut
2013-10-18 2:12 ` Zhu Richard-R65037
2013-10-19 5:07 ` Marek Vasut
2013-10-21 6:33 ` Zhu Richard-R65037
2013-10-18 5:04 ` Tim Harvey
2013-10-15 16:06 ` [PATCH 6/6] PCI: designware: Fix DT resource retrieval Marek Vasut
2013-10-16 0:15 ` Tim Harvey
2013-10-16 3:56 ` Jingoo Han
2013-10-16 14:05 ` Marek Vasut
2013-10-15 16:34 ` [PATCH 0/6] PCI: imx6: Random fixes Marek Vasut
2013-10-16 0:03 ` Jingoo Han
2013-10-16 0:08 ` Marek Vasut
2013-10-29 19:14 ` Bjorn Helgaas
2013-10-30 14:52 ` Marek Vasut
2013-10-30 16:25 ` Bjorn Helgaas
2013-10-31 1:26 ` Shawn Guo
2013-10-31 1:38 ` Jingoo Han
2013-10-31 17:36 ` Bjorn Helgaas
2013-11-11 13:32 ` Jürgen Beisert [this message]
2013-11-11 13:48 ` Marek Vasut
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