From: Marek Vasut <marex@denx.de>
To: Tim Harvey <tharvey@gateworks.com>
Cc: Jingoo Han <jg1.han@samsung.com>,
Pratyush Anand <pratyush.anand@st.com>,
Arnd Bergmann <arnd@arndb.de>,
Mohit KUMAR DCG <Mohit.KUMAR@st.com>,
Richard Zhu <Hong-Xing.Zhu@freescale.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>
Subject: Re: [Query/Discussion]: IO translation with designware PCIe controller
Date: Wed, 11 Dec 2013 00:25:21 +0100 [thread overview]
Message-ID: <201312110025.21570.marex@denx.de> (raw)
In-Reply-To: <CAJ+vNU1LCeSKBjr8ryrJZcPt2+6Xcv0de19FttdpTvSEmr1k_w@mail.gmail.com>
On Wednesday, December 11, 2013 at 12:23:47 AM, Tim Harvey wrote:
> On Tue, Dec 10, 2013 at 2:22 PM, Jingoo Han <jg1.han@samsung.com> wrote:
> > On Tuesday, December 10, 2013 10:27 PM, Marek Vasut wrote:
> >> On Monday, December 09, 2013 at 08:12:42 AM, Pratyush Anand wrote:
> > [.....]
> >
> >> > diff --git a/drivers/pci/host/pcie-designware.c
> >> > b/drivers/pci/host/pcie-designware.c index be6ce30..cf68632 100644
> >> > --- a/drivers/pci/host/pcie-designware.c
> >> > +++ b/drivers/pci/host/pcie-designware.c
> >> > @@ -378,6 +378,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> >> >
> >> > + global_io_offset);
> >> >
> >> > pp->config.io_size = resource_size(&pp->io);
> >> > pp->config.io_bus_addr = range.pci_addr;
> >> >
> >> > + pp->io_base = range.cpu_addr;
> >> >
> >> > }
> >> > if (restype == IORESOURCE_MEM) {
> >> >
> >> > of_pci_range_to_resource(&range, np, &pp->mem);
> >> >
> >> > @@ -403,7 +404,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> >> >
> >> > pp->cfg0_base = pp->cfg.start;
> >> > pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
> >> >
> >> > - pp->io_base = pp->io.start;
> >> >
> >> > pp->mem_base = pp->mem.start;
> >> >
> >> > pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
> >> >
> >> > @@ -667,7 +667,7 @@ static int dw_pcie_setup(int nr, struct
> >> > pci_sys_data *sys)
> >> >
> >> > if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
> >> >
> >> > sys->io_offset = global_io_offset -
> >> > pp->config.io_bus_addr;
> >> >
> >> > - pci_ioremap_io(sys->io_offset, pp->io.start);
> >> > + pci_ioremap_io(sys->io_offset, pp->io_base);
> >> >
> >> > global_io_offset += SZ_64K;
> >> > pci_add_resource_offset(&sys->resources, &pp->io,
> >> >
> >> > sys->io_offset);
> >>
> >> Tim, can you test if this patch fixes your SKY2 IOspace problem please ?
> >
> > Above mentioned patch is NOT the latest patch.
> > Pratyush Anand already submitted the next patch as below.
> >
> > Tim,
> > Would you test the following patch on i.MX6 platform?
> >
> > diff --git a/drivers/pci/host/pcie-designware.c
> > b/drivers/pci/host/pcie-designware.c index be6ce30..b83f5e8 100644
> > --- a/drivers/pci/host/pcie-designware.c
> > +++ b/drivers/pci/host/pcie-designware.c
> > @@ -378,6 +378,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> >
> > + global_io_offset);
> >
> > pp->config.io_size = resource_size(&pp->io);
> > pp->config.io_bus_addr = range.pci_addr;
> >
> > + pp->io_base = range.cpu_addr;
> >
> > }
> > if (restype == IORESOURCE_MEM) {
> >
> > of_pci_range_to_resource(&range, np, &pp->mem);
> >
> > @@ -403,7 +404,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> >
> > pp->cfg0_base = pp->cfg.start;
> > pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
> >
> > - pp->io_base = pp->io.start;
> >
> > pp->mem_base = pp->mem.start;
> >
> > pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
> >
> > @@ -667,7 +667,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data
> > *sys)
> >
> > if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
> >
> > sys->io_offset = global_io_offset -
> > pp->config.io_bus_addr;
> >
> > - pci_ioremap_io(sys->io_offset, pp->io.start);
> > + pci_ioremap_io(global_io_offset, pp->io_base);
> >
> > global_io_offset += SZ_64K;
> > pci_add_resource_offset(&sys->resources, &pp->io,
> >
> > sys->io_offset);
> >
> > Best regards,
> > Jingoo Han
>
> Yes, this patch resolves the issue and now I can use devices with io
> resources behind a bridge attached to the IMX6.
>
> Thanks everyone for your efforts!
This is awesome, thanks guys!
next prev parent reply other threads:[~2013-12-10 23:25 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-05 5:04 [Query/Discussion]: IO translation with designware PCIe controller Pratyush Anand
2013-12-05 21:33 ` Arnd Bergmann
2013-12-06 9:12 ` Pratyush Anand
2013-12-06 14:46 ` Arnd Bergmann
2013-12-09 7:12 ` Pratyush Anand
2013-12-09 16:09 ` Arnd Bergmann
2013-12-10 4:34 ` Pratyush Anand
2013-12-10 5:25 ` Jingoo Han
2013-12-10 6:31 ` Mohit KUMAR DCG
2013-12-10 6:57 ` Pratyush Anand
2013-12-10 7:02 ` Jingoo Han
2013-12-13 7:36 ` Hong-Xing.Zhu
2013-12-10 13:26 ` Marek Vasut
2013-12-10 22:22 ` Jingoo Han
2013-12-10 23:23 ` Tim Harvey
2013-12-10 23:25 ` Marek Vasut [this message]
2013-12-10 23:58 ` Jingoo Han
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