[PATCH v2 0/3] Quirk Intel PCH root ports for ACS-like features

[PATCH v2 0/3] Quirk Intel PCH root ports for ACS-like features

[Alex Williamson]

v2:
 - Remove bus #0 bug in filtering matching
 - Add 2/3 introducing PCI_DEV_FLAGS_ACS_ENABLED_QUIRK, this gives
   is better tracking and addresses the theoretical hotplug issue
 - Update 3/3 for PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
 - Add dev_info to print regardless of whether we changes bits
 - Add Intel cc

As described in 3/3 many Intel root ports lack PCIe ACS capabilities
which results in excessively large IOMMU groups.  Many of these root
ports do provide isolation capabilities, we just need to use device
specific mechanisms to enable and verify.  Long term, I hope we can
round out this list (particularly to include X79 root ports) and
more importantly, encourage proper PCIe ACS support in future
products.  I'm really hoping we can get this in during the 3.14 cycle.
Thanks,

Alex
---

Alex Williamson (3):
      pci: Add device specific PCI ACS enable
      pci: Add pci_dev_flag for ACS enable quirks
      pci/quirks: Enable quirks for PCIe ACS on Intel PCH root ports


 drivers/pci/pci.c    |   26 +++++--
 drivers/pci/quirks.c |  185 ++++++++++++++++++++++++++++++++++++++++++++++++++
 include/linux/pci.h  |    4 +
 3 files changed, 209 insertions(+), 6 deletions(-)

[PATCH v2 1/3] pci: Add device specific PCI ACS enable

[Alex Williamson]

Some devices support PCI ACS-like features, but don't report it using
the standard PCIe capabilities.  We already provide hooks for device
specific testing of ACS, but not for device specific enabling of ACS.
This provides that setup hook.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
---
 drivers/pci/pci.c    |   26 ++++++++++++++++++++------
 drivers/pci/quirks.c |   25 +++++++++++++++++++++++++
 include/linux/pci.h  |    2 ++
 3 files changed, 47 insertions(+), 6 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 1febe90..b89502f 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -2180,21 +2180,18 @@ void pci_request_acs(void)
 }
 
 /**
- * pci_enable_acs - enable ACS if hardware support it
+ * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
  * @dev: the PCI device
  */
-void pci_enable_acs(struct pci_dev *dev)
+static int pci_std_enable_acs(struct pci_dev *dev)
 {
 	int pos;
 	u16 cap;
 	u16 ctrl;
 
-	if (!pci_acs_enable)
-		return;
-
 	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
 	if (!pos)
-		return;
+		return -ENODEV;
 
 	pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
 	pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
@@ -2212,6 +2209,23 @@ void pci_enable_acs(struct pci_dev *dev)
 	ctrl |= (cap & PCI_ACS_UF);
 
 	pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
+
+	return 0;
+}
+
+/**
+ * pci_enable_acs - enable ACS if hardware support it
+ * @dev: the PCI device
+ */
+void pci_enable_acs(struct pci_dev *dev)
+{
+	if (!pci_acs_enable)
+		return;
+
+	if (!pci_std_enable_acs(dev))
+		return;
+
+	pci_dev_specific_enable_acs(dev);
 }
 
 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 5cb726c..f681fb0 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -3461,3 +3461,28 @@ int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
 
 	return -ENOTTY;
 }
+
+static const struct pci_dev_enable_acs {
+	u16 vendor;
+	u16 device;
+	int (*enable_acs)(struct pci_dev *dev);
+} pci_dev_enable_acs[] = {
+	{ 0 }
+};
+
+void pci_dev_specific_enable_acs(struct pci_dev *dev)
+{
+	const struct pci_dev_enable_acs *i;
+	int ret;
+
+	for (i = pci_dev_enable_acs; i->enable_acs; i++) {
+		if ((i->vendor == dev->vendor ||
+		     i->vendor == (u16)PCI_ANY_ID) &&
+		    (i->device == dev->device ||
+		     i->device == (u16)PCI_ANY_ID)) {
+			ret = i->enable_acs(dev);
+			if (ret >= 0)
+				return;
+		}
+	}
+}
diff --git a/include/linux/pci.h b/include/linux/pci.h
index fb57c89..f9a47dd 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1510,6 +1510,7 @@ enum pci_fixup_pass {
 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
 struct pci_dev *pci_get_dma_source(struct pci_dev *dev);
 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
+void pci_dev_specific_enable_acs(struct pci_dev *dev);
 #else
 static inline void pci_fixup_device(enum pci_fixup_pass pass,
 				    struct pci_dev *dev) { }
@@ -1522,6 +1523,7 @@ static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
 {
 	return -ENOTTY;
 }
+static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) {}
 #endif
 
 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);

[PATCH v2 2/3] pci: Add pci_dev_flag for ACS enable quirks

[Alex Williamson]

Quirks that enable ACS compatible functionality on a device need some
way to track whether a given device has been enabled.  Rather than
create new data structures for this, allocate one of the pci_dev_flags
to indicate this setup.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
---
 include/linux/pci.h |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/pci.h b/include/linux/pci.h
index f9a47dd..cb9a109 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -170,6 +170,8 @@ enum pci_dev_flags {
 	PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
 	/* Provide indication device is assigned by a Virtual Machine Manager */
 	PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
+	/* Flag for quirk use to store if quirk specific ACS is enabled */
+	PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) 8,
 };
 
 enum pci_irq_reroute_variant {

[PATCH v2 3/3] pci/quirks: Enable quirks for PCIe ACS on Intel PCH root ports

[Alex Williamson]

Many of the currently available Intel PCH-based root ports do not
provide PCIe ACS capabilities.  Without this, we must assume that
peer-to-peer traffic between multifunction root ports and between
devices behind root ports is possible.  This lack of isolation is
exposed by grouping the devices together in the same IOMMU group.
If we want to expose these devices to userspace, vfio uses IOMMU
groups as the unit of ownership, thus making it very difficult to
assign individual devices to separate users.

The good news is that the chipset does provide ACS-like isolation
capabilities, but we do need to verify and enable those capabilities
if the BIOS has not done so.  This patch implements the device
specific enabling and testing of equivalent ACS function for these
devices.

Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Cc: Don Dugger <donald.d.dugger@intel.com>
---
 drivers/pci/quirks.c |  160 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 160 insertions(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index f681fb0..ed2ed86 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -3423,6 +3423,61 @@ static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
 #endif
 }
 
+/*
+ * Many Intel PCH root ports do provide ACS-like features to disable peer
+ * transactions and validate bus numbers in requests, but do not provide an
+ * actual PCIe ACS capability.  This is the list of device IDs known to fall
+ * into that category as provided by Intel in Red Hat bugzilla 1037684.
+ */
+static const u16 pci_quirk_intel_pch_acs_ids[] = {
+	/* Ibexpeak PCH */
+	0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
+	0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
+	/* Cougarpoint PCH */
+	0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
+	0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
+	/* Pantherpoint PCH */
+	0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
+	0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
+	/* Lynxpoint-H PCH */
+	0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
+	0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
+	/* Lynxpoint-LP PCH */
+	0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
+	0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
+	/* Wildcat PCH */
+	0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
+	0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
+};
+
+static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
+{
+	int i;
+
+	/* Filter out a few obvious non-matches first */
+	if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
+		return false;
+
+	for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
+		if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
+			return true;
+
+	return false;
+}
+
+#define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
+
+static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
+{
+	u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
+		    INTEL_PCH_ACS_FLAGS : 0;
+
+	if (!pci_quirk_intel_pch_acs_match(dev))
+		return -ENOTTY;
+
+	return acs_flags & ~flags ? 0 : 1;
+}
+
 static const struct pci_dev_acs_enabled {
 	u16 vendor;
 	u16 device;
@@ -3434,6 +3489,7 @@ static const struct pci_dev_acs_enabled {
 	{ PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
 	{ PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
 	{ PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
+	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
 	{ 0 }
 };
 
@@ -3462,11 +3518,115 @@ int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
 	return -ENOTTY;
 }
 
+/* Config space offset of Root Complex Base Address register */
+#define INTEL_LPC_RCBA_REG 0xf0
+/* 31:14 RCBA address */
+#define INTEL_LPC_RCBA_MASK 0xffffc000
+/* RCBA Enable */
+#define INTEL_LPC_RCBA_ENABLE (1 << 0)
+
+/* Backbone Scratch Pad Register */
+#define INTEL_BSPR_REG 0x1104
+/* Backbone Peer Non-Posted Disable */
+#define INTEL_BSPR_REG_BPNPD (1 << 8)
+/* Backbone Peer Posted Disable */
+#define INTEL_BSPR_REG_BPPD  (1 << 9)
+
+/* Upstream Peer Decode Configuration Register */
+#define INTEL_UPDCR_REG 0x1114
+/* 5:0 Peer Decode Enable bits */
+#define INTEL_UPDCR_REG_MASK 0x3f
+
+static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
+{
+	u32 rcba, bspr, updcr;
+	void __iomem *rcba_mem;
+
+	/*
+	 * Read the RCBA register from the LPC (D31:F0).  PCH root ports
+	 * are D28:F* and therefore get probed before LPC, thus we can't
+	 * use pci_get_slot/pci_read_config_dword here.
+	 */
+	pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
+				  INTEL_LPC_RCBA_REG, &rcba);
+	if (!(rcba & INTEL_LPC_RCBA_ENABLE))
+		return -EINVAL;
+
+	rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
+				   PAGE_ALIGN(INTEL_UPDCR_REG));
+	if (!rcba_mem)
+		return -ENOMEM;
+
+	/*
+	 * The BSPR can disallow peer cycles, but it's set by soft strap and
+	 * therefore read-only.  If both posted and non-posted peer cycles are
+	 * disallowed, we're ok.  If either are allowed, then we need to use
+	 * the UPDCR to disable peer decodes for each port.  This provides the
+	 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
+	 */
+	bspr = readl(rcba_mem + INTEL_BSPR_REG);
+	bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
+	if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
+		updcr = readl(rcba_mem + INTEL_UPDCR_REG);
+		if (updcr & INTEL_UPDCR_REG_MASK) {
+			dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
+			updcr &= ~INTEL_UPDCR_REG_MASK;
+			writel(updcr, rcba_mem + INTEL_UPDCR_REG);
+		}
+	}
+
+	iounmap(rcba_mem);
+	return 0;
+}
+
+/* Miscellaneous Port Configuration register */
+#define INTEL_MPC_REG 0xd8
+/* MPC: Invalid Receive Bus Number Check Enable */
+#define INTEL_MPC_REG_IRBNCE (1 << 26)
+
+static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
+{
+	u32 mpc;
+
+	/*
+	 * When enabled, the IRBNCE bit of the MPC register enables the
+	 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
+	 * ensures that requester IDs fall within the bus number range
+	 * of the bridge.  Enable if not already.
+	 */
+	pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
+	if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
+		dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
+		mpc |= INTEL_MPC_REG_IRBNCE;
+		pci_write_config_word(dev, INTEL_MPC_REG, mpc);
+	}
+}
+
+static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
+{
+	if (!pci_quirk_intel_pch_acs_match(dev))
+		return -ENOTTY;
+
+	if (pci_quirk_enable_intel_lpc_acs(dev)) {
+		dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
+		return 0;
+	}
+
+	pci_quirk_enable_intel_rp_mpc_acs(dev);
+
+	dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
+
+	dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
+
+	return 0;
+}
+
 static const struct pci_dev_enable_acs {
 	u16 vendor;
 	u16 device;
 	int (*enable_acs)(struct pci_dev *dev);
 } pci_dev_enable_acs[] = {
+	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
 	{ 0 }
 };
 

RE: [PATCH v2 3/3] pci/quirks: Enable quirks for PCIe ACS on Intel PCH root ports

[Dugger, Donald D]

QUNLIC0gdGhpcyBpcyB0aGUgYmVzdCB3YXkgdG8gZGVhbCB3aXRoIHRoaXMgaXNzdWUgdGhhdCB3
ZeKAmXZlIGZvdW5kLg0KDQotLQ0KRG9uIER1Z2dlcg0KIkNlbnNlbyBUb3RvIG5vcyBpbiBLYW5z
YSBlc3NlIGRlY2lzc2UuIiAtIEQuIEdhbGUNClBoOiAzMDMvNDQzLTM3ODYNCg0KLS0tLS1Pcmln
aW5hbCBNZXNzYWdlLS0tLS0NCkZyb206IEFsZXggV2lsbGlhbXNvbiBbbWFpbHRvOmFsZXgud2ls
bGlhbXNvbkByZWRoYXQuY29tXSANClNlbnQ6IE1vbmRheSwgRmVicnVhcnkgMywgMjAxNCAyOjI4
IFBNDQpUbzogYmhlbGdhYXNAZ29vZ2xlLmNvbTsgbGludXgtcGNpQHZnZXIua2VybmVsLm9yZw0K
Q2M6IGxpbnV4LWtlcm5lbEB2Z2VyLmtlcm5lbC5vcmc7IER1Z2dlciwgRG9uYWxkIEQNClN1Ympl
Y3Q6IFtQQVRDSCB2MiAzLzNdIHBjaS9xdWlya3M6IEVuYWJsZSBxdWlya3MgZm9yIFBDSWUgQUNT
IG9uIEludGVsIFBDSCByb290IHBvcnRzDQoNCk1hbnkgb2YgdGhlIGN1cnJlbnRseSBhdmFpbGFi
bGUgSW50ZWwgUENILWJhc2VkIHJvb3QgcG9ydHMgZG8gbm90IHByb3ZpZGUgUENJZSBBQ1MgY2Fw
YWJpbGl0aWVzLiAgV2l0aG91dCB0aGlzLCB3ZSBtdXN0IGFzc3VtZSB0aGF0IHBlZXItdG8tcGVl
ciB0cmFmZmljIGJldHdlZW4gbXVsdGlmdW5jdGlvbiByb290IHBvcnRzIGFuZCBiZXR3ZWVuIGRl
dmljZXMgYmVoaW5kIHJvb3QgcG9ydHMgaXMgcG9zc2libGUuICBUaGlzIGxhY2sgb2YgaXNvbGF0
aW9uIGlzIGV4cG9zZWQgYnkgZ3JvdXBpbmcgdGhlIGRldmljZXMgdG9nZXRoZXIgaW4gdGhlIHNh
bWUgSU9NTVUgZ3JvdXAuDQpJZiB3ZSB3YW50IHRvIGV4cG9zZSB0aGVzZSBkZXZpY2VzIHRvIHVz
ZXJzcGFjZSwgdmZpbyB1c2VzIElPTU1VIGdyb3VwcyBhcyB0aGUgdW5pdCBvZiBvd25lcnNoaXAs
IHRodXMgbWFraW5nIGl0IHZlcnkgZGlmZmljdWx0IHRvIGFzc2lnbiBpbmRpdmlkdWFsIGRldmlj
ZXMgdG8gc2VwYXJhdGUgdXNlcnMuDQoNClRoZSBnb29kIG5ld3MgaXMgdGhhdCB0aGUgY2hpcHNl
dCBkb2VzIHByb3ZpZGUgQUNTLWxpa2UgaXNvbGF0aW9uIGNhcGFiaWxpdGllcywgYnV0IHdlIGRv
IG5lZWQgdG8gdmVyaWZ5IGFuZCBlbmFibGUgdGhvc2UgY2FwYWJpbGl0aWVzIGlmIHRoZSBCSU9T
IGhhcyBub3QgZG9uZSBzby4gIFRoaXMgcGF0Y2ggaW1wbGVtZW50cyB0aGUgZGV2aWNlIHNwZWNp
ZmljIGVuYWJsaW5nIGFuZCB0ZXN0aW5nIG9mIGVxdWl2YWxlbnQgQUNTIGZ1bmN0aW9uIGZvciB0
aGVzZSBkZXZpY2VzLg0KDQpTaWduZWQtb2ZmLWJ5OiBBbGV4IFdpbGxpYW1zb24gPGFsZXgud2ls
bGlhbXNvbkByZWRoYXQuY29tPg0KQ2M6IERvbiBEdWdnZXIgPGRvbmFsZC5kLmR1Z2dlckBpbnRl
bC5jb20+DQotLS0NCiBkcml2ZXJzL3BjaS9xdWlya3MuYyB8ICAxNjAgKysrKysrKysrKysrKysr
KysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysNCiAxIGZpbGUgY2hhbmdlZCwgMTYw
IGluc2VydGlvbnMoKykNCg0KZGlmZiAtLWdpdCBhL2RyaXZlcnMvcGNpL3F1aXJrcy5jIGIvZHJp
dmVycy9wY2kvcXVpcmtzLmMgaW5kZXggZjY4MWZiMC4uZWQyZWQ4NiAxMDA2NDQNCi0tLSBhL2Ry
aXZlcnMvcGNpL3F1aXJrcy5jDQorKysgYi9kcml2ZXJzL3BjaS9xdWlya3MuYw0KQEAgLTM0MjMs
NiArMzQyMyw2MSBAQCBzdGF0aWMgaW50IHBjaV9xdWlya19hbWRfc2JfYWNzKHN0cnVjdCBwY2lf
ZGV2ICpkZXYsIHUxNiBhY3NfZmxhZ3MpICAjZW5kaWYgIH0NCiANCisvKg0KKyAqIE1hbnkgSW50
ZWwgUENIIHJvb3QgcG9ydHMgZG8gcHJvdmlkZSBBQ1MtbGlrZSBmZWF0dXJlcyB0byBkaXNhYmxl
IA0KK3BlZXINCisgKiB0cmFuc2FjdGlvbnMgYW5kIHZhbGlkYXRlIGJ1cyBudW1iZXJzIGluIHJl
cXVlc3RzLCBidXQgZG8gbm90IA0KK3Byb3ZpZGUgYW4NCisgKiBhY3R1YWwgUENJZSBBQ1MgY2Fw
YWJpbGl0eS4gIFRoaXMgaXMgdGhlIGxpc3Qgb2YgZGV2aWNlIElEcyBrbm93biB0byANCitmYWxs
DQorICogaW50byB0aGF0IGNhdGVnb3J5IGFzIHByb3ZpZGVkIGJ5IEludGVsIGluIFJlZCBIYXQg
YnVnemlsbGEgMTAzNzY4NC4NCisgKi8NCitzdGF0aWMgY29uc3QgdTE2IHBjaV9xdWlya19pbnRl
bF9wY2hfYWNzX2lkc1tdID0gew0KKwkvKiBJYmV4cGVhayBQQ0ggKi8NCisJMHgzYjQyLCAweDNi
NDMsIDB4M2I0NCwgMHgzYjQ1LCAweDNiNDYsIDB4M2I0NywgMHgzYjQ4LCAweDNiNDksDQorCTB4
M2I0YSwgMHgzYjRiLCAweDNiNGMsIDB4M2I0ZCwgMHgzYjRlLCAweDNiNGYsIDB4M2I1MCwgMHgz
YjUxLA0KKwkvKiBDb3VnYXJwb2ludCBQQ0ggKi8NCisJMHgxYzEwLCAweDFjMTEsIDB4MWMxMiwg
MHgxYzEzLCAweDFjMTQsIDB4MWMxNSwgMHgxYzE2LCAweDFjMTcsDQorCTB4MWMxOCwgMHgxYzE5
LCAweDFjMWEsIDB4MWMxYiwgMHgxYzFjLCAweDFjMWQsIDB4MWMxZSwgMHgxYzFmLA0KKwkvKiBQ
YW50aGVycG9pbnQgUENIICovDQorCTB4MWUxMCwgMHgxZTExLCAweDFlMTIsIDB4MWUxMywgMHgx
ZTE0LCAweDFlMTUsIDB4MWUxNiwgMHgxZTE3LA0KKwkweDFlMTgsIDB4MWUxOSwgMHgxZTFhLCAw
eDFlMWIsIDB4MWUxYywgMHgxZTFkLCAweDFlMWUsIDB4MWUxZiwNCisJLyogTHlueHBvaW50LUgg
UENIICovDQorCTB4OGMxMCwgMHg4YzExLCAweDhjMTIsIDB4OGMxMywgMHg4YzE0LCAweDhjMTUs
IDB4OGMxNiwgMHg4YzE3LA0KKwkweDhjMTgsIDB4OGMxOSwgMHg4YzFhLCAweDhjMWIsIDB4OGMx
YywgMHg4YzFkLCAweDhjMWUsIDB4OGMxZiwNCisJLyogTHlueHBvaW50LUxQIFBDSCAqLw0KKwkw
eDljMTAsIDB4OWMxMSwgMHg5YzEyLCAweDljMTMsIDB4OWMxNCwgMHg5YzE1LCAweDljMTYsIDB4
OWMxNywNCisJMHg5YzE4LCAweDljMTksIDB4OWMxYSwgMHg5YzFiLA0KKwkvKiBXaWxkY2F0IFBD
SCAqLw0KKwkweDljOTAsIDB4OWM5MSwgMHg5YzkyLCAweDljOTMsIDB4OWM5NCwgMHg5Yzk1LCAw
eDljOTYsIDB4OWM5NywNCisJMHg5Yzk4LCAweDljOTksIDB4OWM5YSwgMHg5YzliLA0KK307DQor
DQorc3RhdGljIGJvb2wgcGNpX3F1aXJrX2ludGVsX3BjaF9hY3NfbWF0Y2goc3RydWN0IHBjaV9k
ZXYgKmRldikgew0KKwlpbnQgaTsNCisNCisJLyogRmlsdGVyIG91dCBhIGZldyBvYnZpb3VzIG5v
bi1tYXRjaGVzIGZpcnN0ICovDQorCWlmICghcGNpX2lzX3BjaWUoZGV2KSB8fCBwY2lfcGNpZV90
eXBlKGRldikgIT0gUENJX0VYUF9UWVBFX1JPT1RfUE9SVCkNCisJCXJldHVybiBmYWxzZTsNCisN
CisJZm9yIChpID0gMDsgaSA8IEFSUkFZX1NJWkUocGNpX3F1aXJrX2ludGVsX3BjaF9hY3NfaWRz
KTsgaSsrKQ0KKwkJaWYgKHBjaV9xdWlya19pbnRlbF9wY2hfYWNzX2lkc1tpXSA9PSBkZXYtPmRl
dmljZSkNCisJCQlyZXR1cm4gdHJ1ZTsNCisNCisJcmV0dXJuIGZhbHNlOw0KK30NCisNCisjZGVm
aW5lIElOVEVMX1BDSF9BQ1NfRkxBR1MgKFBDSV9BQ1NfUlIgfCBQQ0lfQUNTX0NSIHwgUENJX0FD
U19VRiB8IA0KK1BDSV9BQ1NfU1YpDQorDQorc3RhdGljIGludCBwY2lfcXVpcmtfaW50ZWxfcGNo
X2FjcyhzdHJ1Y3QgcGNpX2RldiAqZGV2LCB1MTYgYWNzX2ZsYWdzKSANCit7DQorCXUxNiBmbGFn
cyA9IGRldi0+ZGV2X2ZsYWdzICYgUENJX0RFVl9GTEFHU19BQ1NfRU5BQkxFRF9RVUlSSyA/DQor
CQkgICAgSU5URUxfUENIX0FDU19GTEFHUyA6IDA7DQorDQorCWlmICghcGNpX3F1aXJrX2ludGVs
X3BjaF9hY3NfbWF0Y2goZGV2KSkNCisJCXJldHVybiAtRU5PVFRZOw0KKw0KKwlyZXR1cm4gYWNz
X2ZsYWdzICYgfmZsYWdzID8gMCA6IDE7DQorfQ0KKw0KIHN0YXRpYyBjb25zdCBzdHJ1Y3QgcGNp
X2Rldl9hY3NfZW5hYmxlZCB7DQogCXUxNiB2ZW5kb3I7DQogCXUxNiBkZXZpY2U7DQpAQCAtMzQz
NCw2ICszNDg5LDcgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCBwY2lfZGV2X2Fjc19lbmFibGVkIHsN
CiAJeyBQQ0lfVkVORE9SX0lEX0FUSSwgMHg0MzlkLCBwY2lfcXVpcmtfYW1kX3NiX2FjcyB9LA0K
IAl7IFBDSV9WRU5ET1JfSURfQVRJLCAweDQzODQsIHBjaV9xdWlya19hbWRfc2JfYWNzIH0sDQog
CXsgUENJX1ZFTkRPUl9JRF9BVEksIDB4NDM5OSwgcGNpX3F1aXJrX2FtZF9zYl9hY3MgfSwNCisJ
eyBQQ0lfVkVORE9SX0lEX0lOVEVMLCBQQ0lfQU5ZX0lELCBwY2lfcXVpcmtfaW50ZWxfcGNoX2Fj
cyB9LA0KIAl7IDAgfQ0KIH07DQogDQpAQCAtMzQ2MiwxMSArMzUxOCwxMTUgQEAgaW50IHBjaV9k
ZXZfc3BlY2lmaWNfYWNzX2VuYWJsZWQoc3RydWN0IHBjaV9kZXYgKmRldiwgdTE2IGFjc19mbGFn
cykNCiAJcmV0dXJuIC1FTk9UVFk7DQogfQ0KIA0KKy8qIENvbmZpZyBzcGFjZSBvZmZzZXQgb2Yg
Um9vdCBDb21wbGV4IEJhc2UgQWRkcmVzcyByZWdpc3RlciAqLyAjZGVmaW5lIA0KK0lOVEVMX0xQ
Q19SQ0JBX1JFRyAweGYwDQorLyogMzE6MTQgUkNCQSBhZGRyZXNzICovDQorI2RlZmluZSBJTlRF
TF9MUENfUkNCQV9NQVNLIDB4ZmZmZmMwMDANCisvKiBSQ0JBIEVuYWJsZSAqLw0KKyNkZWZpbmUg
SU5URUxfTFBDX1JDQkFfRU5BQkxFICgxIDw8IDApDQorDQorLyogQmFja2JvbmUgU2NyYXRjaCBQ
YWQgUmVnaXN0ZXIgKi8NCisjZGVmaW5lIElOVEVMX0JTUFJfUkVHIDB4MTEwNA0KKy8qIEJhY2ti
b25lIFBlZXIgTm9uLVBvc3RlZCBEaXNhYmxlICovDQorI2RlZmluZSBJTlRFTF9CU1BSX1JFR19C
UE5QRCAoMSA8PCA4KQ0KKy8qIEJhY2tib25lIFBlZXIgUG9zdGVkIERpc2FibGUgKi8NCisjZGVm
aW5lIElOVEVMX0JTUFJfUkVHX0JQUEQgICgxIDw8IDkpDQorDQorLyogVXBzdHJlYW0gUGVlciBE
ZWNvZGUgQ29uZmlndXJhdGlvbiBSZWdpc3RlciAqLyAjZGVmaW5lIA0KK0lOVEVMX1VQRENSX1JF
RyAweDExMTQNCisvKiA1OjAgUGVlciBEZWNvZGUgRW5hYmxlIGJpdHMgKi8NCisjZGVmaW5lIElO
VEVMX1VQRENSX1JFR19NQVNLIDB4M2YNCisNCitzdGF0aWMgaW50IHBjaV9xdWlya19lbmFibGVf
aW50ZWxfbHBjX2FjcyhzdHJ1Y3QgcGNpX2RldiAqZGV2KSB7DQorCXUzMiByY2JhLCBic3ByLCB1
cGRjcjsNCisJdm9pZCBfX2lvbWVtICpyY2JhX21lbTsNCisNCisJLyoNCisJICogUmVhZCB0aGUg
UkNCQSByZWdpc3RlciBmcm9tIHRoZSBMUEMgKEQzMTpGMCkuICBQQ0ggcm9vdCBwb3J0cw0KKwkg
KiBhcmUgRDI4OkYqIGFuZCB0aGVyZWZvcmUgZ2V0IHByb2JlZCBiZWZvcmUgTFBDLCB0aHVzIHdl
IGNhbid0DQorCSAqIHVzZSBwY2lfZ2V0X3Nsb3QvcGNpX3JlYWRfY29uZmlnX2R3b3JkIGhlcmUu
DQorCSAqLw0KKwlwY2lfYnVzX3JlYWRfY29uZmlnX2R3b3JkKGRldi0+YnVzLCBQQ0lfREVWRk4o
MzEsIDApLA0KKwkJCQkgIElOVEVMX0xQQ19SQ0JBX1JFRywgJnJjYmEpOw0KKwlpZiAoIShyY2Jh
ICYgSU5URUxfTFBDX1JDQkFfRU5BQkxFKSkNCisJCXJldHVybiAtRUlOVkFMOw0KKw0KKwlyY2Jh
X21lbSA9IGlvcmVtYXBfbm9jYWNoZShyY2JhICYgSU5URUxfTFBDX1JDQkFfTUFTSywNCisJCQkJ
ICAgUEFHRV9BTElHTihJTlRFTF9VUERDUl9SRUcpKTsNCisJaWYgKCFyY2JhX21lbSkNCisJCXJl
dHVybiAtRU5PTUVNOw0KKw0KKwkvKg0KKwkgKiBUaGUgQlNQUiBjYW4gZGlzYWxsb3cgcGVlciBj
eWNsZXMsIGJ1dCBpdCdzIHNldCBieSBzb2Z0IHN0cmFwIGFuZA0KKwkgKiB0aGVyZWZvcmUgcmVh
ZC1vbmx5LiAgSWYgYm90aCBwb3N0ZWQgYW5kIG5vbi1wb3N0ZWQgcGVlciBjeWNsZXMgYXJlDQor
CSAqIGRpc2FsbG93ZWQsIHdlJ3JlIG9rLiAgSWYgZWl0aGVyIGFyZSBhbGxvd2VkLCB0aGVuIHdl
IG5lZWQgdG8gdXNlDQorCSAqIHRoZSBVUERDUiB0byBkaXNhYmxlIHBlZXIgZGVjb2RlcyBmb3Ig
ZWFjaCBwb3J0LiAgVGhpcyBwcm92aWRlcyB0aGUNCisJICogUENJZSBBQ1MgZXF1aXZhbGVudCBv
ZiBQQ0lfQUNTX1JSIHwgUENJX0FDU19DUiB8IFBDSV9BQ1NfVUYNCisJICovDQorCWJzcHIgPSBy
ZWFkbChyY2JhX21lbSArIElOVEVMX0JTUFJfUkVHKTsNCisJYnNwciAmPSBJTlRFTF9CU1BSX1JF
R19CUE5QRCB8IElOVEVMX0JTUFJfUkVHX0JQUEQ7DQorCWlmIChic3ByICE9IChJTlRFTF9CU1BS
X1JFR19CUE5QRCB8IElOVEVMX0JTUFJfUkVHX0JQUEQpKSB7DQorCQl1cGRjciA9IHJlYWRsKHJj
YmFfbWVtICsgSU5URUxfVVBEQ1JfUkVHKTsNCisJCWlmICh1cGRjciAmIElOVEVMX1VQRENSX1JF
R19NQVNLKSB7DQorCQkJZGV2X2luZm8oJmRldi0+ZGV2LCAiRGlzYWJsaW5nIFVQRENSIHBlZXIg
ZGVjb2Rlc1xuIik7DQorCQkJdXBkY3IgJj0gfklOVEVMX1VQRENSX1JFR19NQVNLOw0KKwkJCXdy
aXRlbCh1cGRjciwgcmNiYV9tZW0gKyBJTlRFTF9VUERDUl9SRUcpOw0KKwkJfQ0KKwl9DQorDQor
CWlvdW5tYXAocmNiYV9tZW0pOw0KKwlyZXR1cm4gMDsNCit9DQorDQorLyogTWlzY2VsbGFuZW91
cyBQb3J0IENvbmZpZ3VyYXRpb24gcmVnaXN0ZXIgKi8gI2RlZmluZSBJTlRFTF9NUENfUkVHIA0K
KzB4ZDgNCisvKiBNUEM6IEludmFsaWQgUmVjZWl2ZSBCdXMgTnVtYmVyIENoZWNrIEVuYWJsZSAq
LyAjZGVmaW5lIA0KK0lOVEVMX01QQ19SRUdfSVJCTkNFICgxIDw8IDI2KQ0KKw0KK3N0YXRpYyB2
b2lkIHBjaV9xdWlya19lbmFibGVfaW50ZWxfcnBfbXBjX2FjcyhzdHJ1Y3QgcGNpX2RldiAqZGV2
KSB7DQorCXUzMiBtcGM7DQorDQorCS8qDQorCSAqIFdoZW4gZW5hYmxlZCwgdGhlIElSQk5DRSBi
aXQgb2YgdGhlIE1QQyByZWdpc3RlciBlbmFibGVzIHRoZQ0KKwkgKiBlcXVpdmFsZW50IG9mIFBD
SSBBQ1MgU291cmNlIFZhbGlkYXRpb24gKFBDSV9BQ1NfU1YpLCB3aGljaA0KKwkgKiBlbnN1cmVz
IHRoYXQgcmVxdWVzdGVyIElEcyBmYWxsIHdpdGhpbiB0aGUgYnVzIG51bWJlciByYW5nZQ0KKwkg
KiBvZiB0aGUgYnJpZGdlLiAgRW5hYmxlIGlmIG5vdCBhbHJlYWR5Lg0KKwkgKi8NCisJcGNpX3Jl
YWRfY29uZmlnX2R3b3JkKGRldiwgSU5URUxfTVBDX1JFRywgJm1wYyk7DQorCWlmICghKG1wYyAm
IElOVEVMX01QQ19SRUdfSVJCTkNFKSkgew0KKwkJZGV2X2luZm8oJmRldi0+ZGV2LCAiRW5hYmxp
bmcgTVBDIElSQk5DRVxuIik7DQorCQltcGMgfD0gSU5URUxfTVBDX1JFR19JUkJOQ0U7DQorCQlw
Y2lfd3JpdGVfY29uZmlnX3dvcmQoZGV2LCBJTlRFTF9NUENfUkVHLCBtcGMpOw0KKwl9DQorfQ0K
Kw0KK3N0YXRpYyBpbnQgcGNpX3F1aXJrX2VuYWJsZV9pbnRlbF9wY2hfYWNzKHN0cnVjdCBwY2lf
ZGV2ICpkZXYpIHsNCisJaWYgKCFwY2lfcXVpcmtfaW50ZWxfcGNoX2Fjc19tYXRjaChkZXYpKQ0K
KwkJcmV0dXJuIC1FTk9UVFk7DQorDQorCWlmIChwY2lfcXVpcmtfZW5hYmxlX2ludGVsX2xwY19h
Y3MoZGV2KSkgew0KKwkJZGV2X3dhcm4oJmRldi0+ZGV2LCAiRmFpbGVkIHRvIGVuYWJsZSBJbnRl
bCBQQ0ggQUNTIHF1aXJrXG4iKTsNCisJCXJldHVybiAwOw0KKwl9DQorDQorCXBjaV9xdWlya19l
bmFibGVfaW50ZWxfcnBfbXBjX2FjcyhkZXYpOw0KKw0KKwlkZXYtPmRldl9mbGFncyB8PSBQQ0lf
REVWX0ZMQUdTX0FDU19FTkFCTEVEX1FVSVJLOw0KKw0KKwlkZXZfaW5mbygmZGV2LT5kZXYsICJJ
bnRlbCBQQ0ggcm9vdCBwb3J0IEFDUyB3b3JrYXJvdW5kIGVuYWJsZWRcbiIpOw0KKw0KKwlyZXR1
cm4gMDsNCit9DQorDQogc3RhdGljIGNvbnN0IHN0cnVjdCBwY2lfZGV2X2VuYWJsZV9hY3Mgew0K
IAl1MTYgdmVuZG9yOw0KIAl1MTYgZGV2aWNlOw0KIAlpbnQgKCplbmFibGVfYWNzKShzdHJ1Y3Qg
cGNpX2RldiAqZGV2KTsgIH0gcGNpX2Rldl9lbmFibGVfYWNzW10gPSB7DQorCXsgUENJX1ZFTkRP
Ul9JRF9JTlRFTCwgUENJX0FOWV9JRCwgcGNpX3F1aXJrX2VuYWJsZV9pbnRlbF9wY2hfYWNzIH0s
DQogCXsgMCB9DQogfTsNCiANCg0K

Re: [PATCH v2 0/3] Quirk Intel PCH root ports for ACS-like features

[Bjorn Helgaas]

[+cc Don]

On Mon, Feb 03, 2014 at 02:27:27PM -0700, Alex Williamson wrote:
> v2:
>  - Remove bus #0 bug in filtering matching
>  - Add 2/3 introducing PCI_DEV_FLAGS_ACS_ENABLED_QUIRK, this gives
>    is better tracking and addresses the theoretical hotplug issue
>  - Update 3/3 for PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
>  - Add dev_info to print regardless of whether we changes bits
>  - Add Intel cc
>
> As described in 3/3 many Intel root ports lack PCIe ACS capabilities
> which results in excessively large IOMMU groups.  Many of these root
> ports do provide isolation capabilities, we just need to use device
> specific mechanisms to enable and verify.  Long term, I hope we can
> round out this list (particularly to include X79 root ports) and
> more importantly, encourage proper PCIe ACS support in future
> products.  I'm really hoping we can get this in during the 3.14 cycle.
> Thanks,
>
> Alex
> ---
>
> Alex Williamson (3):
>       pci: Add device specific PCI ACS enable
>       pci: Add pci_dev_flag for ACS enable quirks
>       pci/quirks: Enable quirks for PCIe ACS on Intel PCH root ports

I applied these (with Don's ack for 3/3) to pci/virtualization.

I tried to figure out how to handle post-merge window patches.  Per
Documentation/development-process/2.Process, "[after -rc1], only patches
which fix problems should be submitted to the mainline," so one might
conclude that a fix for any sort of problem is allowed.  However,
Documentation/networking/netdev-FAQ.txt says "No new features get mainlined
after this [-rc1] -- only fixes to the rc1 content are expected," which is
how I've been operating.

In any case, these patches look more like new functionality (enabling a
non-standard ACS feature) than a bug fix to me, so my preference is to
merge them during the v3.15 merge window.

I understand the desire for v3.14, namely, "lots of Intel devices don't
support ACS, and that makes it hard for users to expose devices to
userspace with fine granularity, and waiting for v3.15 will mean another
two months."  But this problem is really of Intel's own making: if they'd
used standard ACS, or if they'd documented their non-standard mechanism,
this wouldn't be an issue.

Bjorn

RE: [PATCH v2 0/3] Quirk Intel PCH root ports for ACS-like features

[Dugger, Donald D]

SW4gcmU6IEZlYXR1cmUgdnMuIGJ1ZyBmaXgNCg0KQXQgdGhlIHJpc2sgb2YgdHJ5aW5nIHRvIGFy
Z3VpbmcgYWJvdXQgdGhlIG1lYW5pbmcgb2YgYGlzJyBJIHdvdWxkIGFyZ3VlIHRoYXQgdGhpcyBp
cyBtb3JlIGEgYnVnIGZpeCB0aGFuIGEgZmVhdHVyZS4gIFdlJ3JlIG5vdCBhZGRpbmcgYSBuZXcg
Y2FwYWJpbGl0eSwgd2UgYXJlIHRyeWluZyB0byB3b3JrIGFyb3VuZCBkZWZpY2llbnQgSFcgKG5v
IGFyZ3VtZW50IHRoYXQgd2Ugc2hvdWxkIGhhdmUgaW1wbGVtZW50ZWQgQUNTIG9uIGFsbCBwbGF0
Zm9ybXMpLg0KDQpIYXZpbmcgc2FpZCB0aGF0LCBhbHRob3VnaCBJIHdvdWxkIG9idmlvdXNseSBw
cmVmZXIgdG8gc2VlIHRoaXMgaW4gdjMuMTQgd2UgY2FuIGxpdmUgd2l0aCB0aGlzIGhpdHRpbmcg
djMuMTUuDQoNCi0tDQpEb24gRHVnZ2VyDQoiQ2Vuc2VvIFRvdG8gbm9zIGluIEthbnNhIGVzc2Ug
ZGVjaXNzZS4iIC0gRC4gR2FsZQ0KUGg6IDMwMy80NDMtMzc4Ng0KDQotLS0tLU9yaWdpbmFsIE1l
c3NhZ2UtLS0tLQ0KRnJvbTogQmpvcm4gSGVsZ2FhcyBbbWFpbHRvOmJoZWxnYWFzQGdvb2dsZS5j
b21dIA0KU2VudDogRnJpZGF5LCBGZWJydWFyeSAxNCwgMjAxNCAyOjQzIFBNDQpUbzogQWxleCBX
aWxsaWFtc29uDQpDYzogbGludXgtcGNpQHZnZXIua2VybmVsLm9yZzsgbGludXgta2VybmVsQHZn
ZXIua2VybmVsLm9yZzsgRHVnZ2VyLCBEb25hbGQgRA0KU3ViamVjdDogUmU6IFtQQVRDSCB2MiAw
LzNdIFF1aXJrIEludGVsIFBDSCByb290IHBvcnRzIGZvciBBQ1MtbGlrZSBmZWF0dXJlcw0KDQpb
K2NjIERvbl0NCg0KT24gTW9uLCBGZWIgMDMsIDIwMTQgYXQgMDI6Mjc6MjdQTSAtMDcwMCwgQWxl
eCBXaWxsaWFtc29uIHdyb3RlOg0KPiB2MjoNCj4gIC0gUmVtb3ZlIGJ1cyAjMCBidWcgaW4gZmls
dGVyaW5nIG1hdGNoaW5nDQo+ICAtIEFkZCAyLzMgaW50cm9kdWNpbmcgUENJX0RFVl9GTEFHU19B
Q1NfRU5BQkxFRF9RVUlSSywgdGhpcyBnaXZlcw0KPiAgICBpcyBiZXR0ZXIgdHJhY2tpbmcgYW5k
IGFkZHJlc3NlcyB0aGUgdGhlb3JldGljYWwgaG90cGx1ZyBpc3N1ZQ0KPiAgLSBVcGRhdGUgMy8z
IGZvciBQQ0lfREVWX0ZMQUdTX0FDU19FTkFCTEVEX1FVSVJLDQo+ICAtIEFkZCBkZXZfaW5mbyB0
byBwcmludCByZWdhcmRsZXNzIG9mIHdoZXRoZXIgd2UgY2hhbmdlcyBiaXRzDQo+ICAtIEFkZCBJ
bnRlbCBjYw0KPg0KPiBBcyBkZXNjcmliZWQgaW4gMy8zIG1hbnkgSW50ZWwgcm9vdCBwb3J0cyBs
YWNrIFBDSWUgQUNTIGNhcGFiaWxpdGllcyANCj4gd2hpY2ggcmVzdWx0cyBpbiBleGNlc3NpdmVs
eSBsYXJnZSBJT01NVSBncm91cHMuICBNYW55IG9mIHRoZXNlIHJvb3QgDQo+IHBvcnRzIGRvIHBy
b3ZpZGUgaXNvbGF0aW9uIGNhcGFiaWxpdGllcywgd2UganVzdCBuZWVkIHRvIHVzZSBkZXZpY2Ug
DQo+IHNwZWNpZmljIG1lY2hhbmlzbXMgdG8gZW5hYmxlIGFuZCB2ZXJpZnkuICBMb25nIHRlcm0s
IEkgaG9wZSB3ZSBjYW4gDQo+IHJvdW5kIG91dCB0aGlzIGxpc3QgKHBhcnRpY3VsYXJseSB0byBp
bmNsdWRlIFg3OSByb290IHBvcnRzKSBhbmQgbW9yZSANCj4gaW1wb3J0YW50bHksIGVuY291cmFn
ZSBwcm9wZXIgUENJZSBBQ1Mgc3VwcG9ydCBpbiBmdXR1cmUgcHJvZHVjdHMuICANCj4gSSdtIHJl
YWxseSBob3Bpbmcgd2UgY2FuIGdldCB0aGlzIGluIGR1cmluZyB0aGUgMy4xNCBjeWNsZS4NCj4g
VGhhbmtzLA0KPg0KPiBBbGV4DQo+IC0tLQ0KPg0KPiBBbGV4IFdpbGxpYW1zb24gKDMpOg0KPiAg
ICAgICBwY2k6IEFkZCBkZXZpY2Ugc3BlY2lmaWMgUENJIEFDUyBlbmFibGUNCj4gICAgICAgcGNp
OiBBZGQgcGNpX2Rldl9mbGFnIGZvciBBQ1MgZW5hYmxlIHF1aXJrcw0KPiAgICAgICBwY2kvcXVp
cmtzOiBFbmFibGUgcXVpcmtzIGZvciBQQ0llIEFDUyBvbiBJbnRlbCBQQ0ggcm9vdCBwb3J0cw0K
DQpJIGFwcGxpZWQgdGhlc2UgKHdpdGggRG9uJ3MgYWNrIGZvciAzLzMpIHRvIHBjaS92aXJ0dWFs
aXphdGlvbi4NCg0KSSB0cmllZCB0byBmaWd1cmUgb3V0IGhvdyB0byBoYW5kbGUgcG9zdC1tZXJn
ZSB3aW5kb3cgcGF0Y2hlcy4gIFBlciBEb2N1bWVudGF0aW9uL2RldmVsb3BtZW50LXByb2Nlc3Mv
Mi5Qcm9jZXNzLCAiW2FmdGVyIC1yYzFdLCBvbmx5IHBhdGNoZXMgd2hpY2ggZml4IHByb2JsZW1z
IHNob3VsZCBiZSBzdWJtaXR0ZWQgdG8gdGhlIG1haW5saW5lLCIgc28gb25lIG1pZ2h0IGNvbmNs
dWRlIHRoYXQgYSBmaXggZm9yIGFueSBzb3J0IG9mIHByb2JsZW0gaXMgYWxsb3dlZC4gIEhvd2V2
ZXIsIERvY3VtZW50YXRpb24vbmV0d29ya2luZy9uZXRkZXYtRkFRLnR4dCBzYXlzICJObyBuZXcg
ZmVhdHVyZXMgZ2V0IG1haW5saW5lZCBhZnRlciB0aGlzIFstcmMxXSAtLSBvbmx5IGZpeGVzIHRv
IHRoZSByYzEgY29udGVudCBhcmUgZXhwZWN0ZWQsIiB3aGljaCBpcyBob3cgSSd2ZSBiZWVuIG9w
ZXJhdGluZy4NCg0KSW4gYW55IGNhc2UsIHRoZXNlIHBhdGNoZXMgbG9vayBtb3JlIGxpa2UgbmV3
IGZ1bmN0aW9uYWxpdHkgKGVuYWJsaW5nIGEgbm9uLXN0YW5kYXJkIEFDUyBmZWF0dXJlKSB0aGFu
IGEgYnVnIGZpeCB0byBtZSwgc28gbXkgcHJlZmVyZW5jZSBpcyB0byBtZXJnZSB0aGVtIGR1cmlu
ZyB0aGUgdjMuMTUgbWVyZ2Ugd2luZG93Lg0KDQpJIHVuZGVyc3RhbmQgdGhlIGRlc2lyZSBmb3Ig
djMuMTQsIG5hbWVseSwgImxvdHMgb2YgSW50ZWwgZGV2aWNlcyBkb24ndCBzdXBwb3J0IEFDUywg
YW5kIHRoYXQgbWFrZXMgaXQgaGFyZCBmb3IgdXNlcnMgdG8gZXhwb3NlIGRldmljZXMgdG8gdXNl
cnNwYWNlIHdpdGggZmluZSBncmFudWxhcml0eSwgYW5kIHdhaXRpbmcgZm9yIHYzLjE1IHdpbGwg
bWVhbiBhbm90aGVyIHR3byBtb250aHMuIiAgQnV0IHRoaXMgcHJvYmxlbSBpcyByZWFsbHkgb2Yg
SW50ZWwncyBvd24gbWFraW5nOiBpZiB0aGV5J2QgdXNlZCBzdGFuZGFyZCBBQ1MsIG9yIGlmIHRo
ZXknZCBkb2N1bWVudGVkIHRoZWlyIG5vbi1zdGFuZGFyZCBtZWNoYW5pc20sIHRoaXMgd291bGRu
J3QgYmUgYW4gaXNzdWUuDQoNCkJqb3JuDQo=

Re: [PATCH v2 0/3] Quirk Intel PCH root ports for ACS-like features

[Alex Williamson]

On Fri, 2014-02-14 at 14:43 -0700, Bjorn Helgaas wrote:
> [+cc Don]
> 
> On Mon, Feb 03, 2014 at 02:27:27PM -0700, Alex Williamson wrote:
> > v2:
> >  - Remove bus #0 bug in filtering matching
> >  - Add 2/3 introducing PCI_DEV_FLAGS_ACS_ENABLED_QUIRK, this gives
> >    is better tracking and addresses the theoretical hotplug issue
> >  - Update 3/3 for PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
> >  - Add dev_info to print regardless of whether we changes bits
> >  - Add Intel cc
> >
> > As described in 3/3 many Intel root ports lack PCIe ACS capabilities
> > which results in excessively large IOMMU groups.  Many of these root
> > ports do provide isolation capabilities, we just need to use device
> > specific mechanisms to enable and verify.  Long term, I hope we can
> > round out this list (particularly to include X79 root ports) and
> > more importantly, encourage proper PCIe ACS support in future
> > products.  I'm really hoping we can get this in during the 3.14 cycle.
> > Thanks,
> >
> > Alex
> > ---
> >
> > Alex Williamson (3):
> >       pci: Add device specific PCI ACS enable
> >       pci: Add pci_dev_flag for ACS enable quirks
> >       pci/quirks: Enable quirks for PCIe ACS on Intel PCH root ports
> 
> I applied these (with Don's ack for 3/3) to pci/virtualization.
> 
> I tried to figure out how to handle post-merge window patches.  Per
> Documentation/development-process/2.Process, "[after -rc1], only patches
> which fix problems should be submitted to the mainline," so one might
> conclude that a fix for any sort of problem is allowed.  However,
> Documentation/networking/netdev-FAQ.txt says "No new features get mainlined
> after this [-rc1] -- only fixes to the rc1 content are expected," which is
> how I've been operating.
> 
> In any case, these patches look more like new functionality (enabling a
> non-standard ACS feature) than a bug fix to me, so my preference is to
> merge them during the v3.15 merge window.
> 
> I understand the desire for v3.14, namely, "lots of Intel devices don't
> support ACS, and that makes it hard for users to expose devices to
> userspace with fine granularity, and waiting for v3.15 will mean another
> two months."  But this problem is really of Intel's own making: if they'd
> used standard ACS, or if they'd documented their non-standard mechanism,
> this wouldn't be an issue.

I appreciate you taking the time to consider it for 3.14.  I'll look
forward to it appearing in linux-next for 3.15.  Thanks for review and
applying,

Alex