* [PATCH 1/1] Designware:RC BARs setup related fix
@ 2014-02-19 12:04 Mohit Kumar
2014-02-19 21:53 ` Bjorn Helgaas
0 siblings, 1 reply; 6+ messages in thread
From: Mohit Kumar @ 2014-02-19 12:04 UTC (permalink / raw)
To: jg1.han; +Cc: Mohit Kumar, Pratyush Anand, Arnd Bergmann, spear-devel,
linux-pci
The Synopsys PCIe core provides one pair of 32-bit BARs (BAR 0 and BAR 1).
The BARs can be configured as follows:
- One 64-bit BAR: BARs 0 and 1 are combined to form a single 64-bit BAR.
- Two 32-bit BARs: BARs 0 and 1 are two independent 32-bit BARs
This patch corrects 64-bit, non-prefetchable memory BAR configuration
implemented in dw driver.
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: spear-devel@list.st.com
Cc: linux-pci@vger.kernel.org
---
drivers/pci/host/pcie-designware.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 17ce88f..6d23d8c 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -800,7 +800,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
/* setup RC BARs */
dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
- dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_1);
+ dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
/* setup interrupt pins */
dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
--
1.7.0.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/1] Designware:RC BARs setup related fix
2014-02-19 12:04 [PATCH 1/1] Designware:RC BARs setup related fix Mohit Kumar
@ 2014-02-19 21:53 ` Bjorn Helgaas
2014-02-20 4:13 ` Mohit KUMAR DCG
0 siblings, 1 reply; 6+ messages in thread
From: Bjorn Helgaas @ 2014-02-19 21:53 UTC (permalink / raw)
To: Mohit Kumar
Cc: jg1.han, Pratyush Anand, Arnd Bergmann, spear-devel, linux-pci
On Wed, Feb 19, 2014 at 05:34:35PM +0530, Mohit Kumar wrote:
> The Synopsys PCIe core provides one pair of 32-bit BARs (BAR 0 and BAR 1).
> The BARs can be configured as follows:
>
> - One 64-bit BAR: BARs 0 and 1 are combined to form a single 64-bit BAR.
> - Two 32-bit BARs: BARs 0 and 1 are two independent 32-bit BARs
>
> This patch corrects 64-bit, non-prefetchable memory BAR configuration
> implemented in dw driver.
>
> Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
> Cc: Pratyush Anand <pratyush.anand@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: spear-devel@list.st.com
> Cc: linux-pci@vger.kernel.org
Applied to pci/host-designware for v3.15, thanks!
I update the summary to the following; let me know if it's not accurate:
PCI: designware: Fix RC BAR to be single 64-bit non-prefetchable memory BAR
> ---
> drivers/pci/host/pcie-designware.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 17ce88f..6d23d8c 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -800,7 +800,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>
> /* setup RC BARs */
> dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
> - dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_1);
> + dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
>
> /* setup interrupt pins */
> dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
> --
> 1.7.0.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH 1/1] Designware:RC BARs setup related fix
2014-02-19 21:53 ` Bjorn Helgaas
@ 2014-02-20 4:13 ` Mohit KUMAR DCG
2014-02-20 6:45 ` Mohit KUMAR DCG
0 siblings, 1 reply; 6+ messages in thread
From: Mohit KUMAR DCG @ 2014-02-20 4:13 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: jg1.han@samsung.com, Pratyush ANAND, Arnd Bergmann, spear-devel,
linux-pci@vger.kernel.org
Hello Bjorn,
> -----Original Message-----
> From: Bjorn Helgaas [mailto:bhelgaas@google.com]
> Sent: Thursday, February 20, 2014 3:24 AM
> To: Mohit KUMAR DCG
> Cc: jg1.han@samsung.com; Pratyush ANAND; Arnd Bergmann; spear-devel;
> linux-pci@vger.kernel.org
> Subject: Re: [PATCH 1/1] Designware:RC BARs setup related fix
>
> On Wed, Feb 19, 2014 at 05:34:35PM +0530, Mohit Kumar wrote:
> > The Synopsys PCIe core provides one pair of 32-bit BARs (BAR 0 and BAR
> 1).
> > The BARs can be configured as follows:
> >
> > - One 64-bit BAR: BARs 0 and 1 are combined to form a single 64-bit BAR.
> > - Two 32-bit BARs: BARs 0 and 1 are two independent 32-bit BARs
> >
> > This patch corrects 64-bit, non-prefetchable memory BAR configuration
> > implemented in dw driver.
> >
> > Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
> > Cc: Pratyush Anand <pratyush.anand@st.com>
> > Cc: Jingoo Han <jg1.han@samsung.com>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: spear-devel@list.st.com
> > Cc: linux-pci@vger.kernel.org
>
> Applied to pci/host-designware for v3.15, thanks!
- thanks
>
> I update the summary to the following; let me know if it's not accurate:
>
> PCI: designware: Fix RC BAR to be single 64-bit non-prefetchable memory
> BAR
- yes, it looks better
Thanks,
Mohit
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH 1/1] Designware:RC BARs setup related fix
2014-02-20 4:13 ` Mohit KUMAR DCG
@ 2014-02-20 6:45 ` Mohit KUMAR DCG
2014-02-20 19:26 ` Bjorn Helgaas
0 siblings, 1 reply; 6+ messages in thread
From: Mohit KUMAR DCG @ 2014-02-20 6:45 UTC (permalink / raw)
To: Bjorn Helgaas, stable@vger.kerne.org
Cc: jg1.han@samsung.com, Pratyush ANAND, Arnd Bergmann, spear-devel,
linux-pci@vger.kernel.org
+cc stable@vger.kerne.org
> -----Original Message-----
> From: Mohit KUMAR [mailto:mohit.kumar@st.com]
> Sent: Thursday, February 20, 2014 9:43 AM
> To: Bjorn Helgaas
> Cc: jg1.han@samsung.com; Pratyush ANAND; Arnd Bergmann; spear-devel;
> linux-pci@vger.kernel.org
> Subject: RE: [PATCH 1/1] Designware:RC BARs setup related fix
>
> Hello Bjorn,
>
> > -----Original Message-----
> > From: Bjorn Helgaas [mailto:bhelgaas@google.com]
> > Sent: Thursday, February 20, 2014 3:24 AM
> > To: Mohit KUMAR DCG
> > Cc: jg1.han@samsung.com; Pratyush ANAND; Arnd Bergmann; spear-
> devel;
> > linux-pci@vger.kernel.org
> > Subject: Re: [PATCH 1/1] Designware:RC BARs setup related fix
> >
> > On Wed, Feb 19, 2014 at 05:34:35PM +0530, Mohit Kumar wrote:
> > > The Synopsys PCIe core provides one pair of 32-bit BARs (BAR 0 and
> > > BAR
> > 1).
> > > The BARs can be configured as follows:
> > >
> > > - One 64-bit BAR: BARs 0 and 1 are combined to form a single 64-bit BAR.
> > > - Two 32-bit BARs: BARs 0 and 1 are two independent 32-bit BARs
> > >
> > > This patch corrects 64-bit, non-prefetchable memory BAR
> > > configuration implemented in dw driver.
> > >
> > > Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
> > > Cc: Pratyush Anand <pratyush.anand@st.com>
> > > Cc: Jingoo Han <jg1.han@samsung.com>
> > > Cc: Arnd Bergmann <arnd@arndb.de>
> > > Cc: spear-devel@list.st.com
> > > Cc: linux-pci@vger.kernel.org
> >
> > Applied to pci/host-designware for v3.15, thanks!
>
> - thanks
>
> >
> > I update the summary to the following; let me know if it's not accurate:
> >
> > PCI: designware: Fix RC BAR to be single 64-bit non-prefetchable
> > memory BAR
>
> - yes, it looks better
>
> Thanks,
> Mohit
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/1] Designware:RC BARs setup related fix
2014-02-20 6:45 ` Mohit KUMAR DCG
@ 2014-02-20 19:26 ` Bjorn Helgaas
0 siblings, 0 replies; 6+ messages in thread
From: Bjorn Helgaas @ 2014-02-20 19:26 UTC (permalink / raw)
To: Mohit KUMAR DCG
Cc: jg1.han@samsung.com, Pratyush ANAND, Arnd Bergmann, spear-devel,
linux-pci@vger.kernel.org
On Wed, Feb 19, 2014 at 11:45 PM, Mohit KUMAR DCG <Mohit.KUMAR@st.com> wrote:
> +cc stable@vger.kerne.org
I assume you meant that you want this patch to go to the stable
kernels? I added the appropriate tag to the patch:
Cc: stable@vger.kernel.org # v3.12+
This won't apply cleanly to v3.11 because there were unrelated changes
to these lines. If you want it in v3.11, please send the appropriate
patch to stable@vger.kernel.org.
Bjorn
>> -----Original Message-----
>> From: Mohit KUMAR [mailto:mohit.kumar@st.com]
>> Sent: Thursday, February 20, 2014 9:43 AM
>> To: Bjorn Helgaas
>> Cc: jg1.han@samsung.com; Pratyush ANAND; Arnd Bergmann; spear-devel;
>> linux-pci@vger.kernel.org
>> Subject: RE: [PATCH 1/1] Designware:RC BARs setup related fix
>>
>> Hello Bjorn,
>>
>> > -----Original Message-----
>> > From: Bjorn Helgaas [mailto:bhelgaas@google.com]
>> > Sent: Thursday, February 20, 2014 3:24 AM
>> > To: Mohit KUMAR DCG
>> > Cc: jg1.han@samsung.com; Pratyush ANAND; Arnd Bergmann; spear-
>> devel;
>> > linux-pci@vger.kernel.org
>> > Subject: Re: [PATCH 1/1] Designware:RC BARs setup related fix
>> >
>> > On Wed, Feb 19, 2014 at 05:34:35PM +0530, Mohit Kumar wrote:
>> > > The Synopsys PCIe core provides one pair of 32-bit BARs (BAR 0 and
>> > > BAR
>> > 1).
>> > > The BARs can be configured as follows:
>> > >
>> > > - One 64-bit BAR: BARs 0 and 1 are combined to form a single 64-bit BAR.
>> > > - Two 32-bit BARs: BARs 0 and 1 are two independent 32-bit BARs
>> > >
>> > > This patch corrects 64-bit, non-prefetchable memory BAR
>> > > configuration implemented in dw driver.
>> > >
>> > > Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
>> > > Cc: Pratyush Anand <pratyush.anand@st.com>
>> > > Cc: Jingoo Han <jg1.han@samsung.com>
>> > > Cc: Arnd Bergmann <arnd@arndb.de>
>> > > Cc: spear-devel@list.st.com
>> > > Cc: linux-pci@vger.kernel.org
>> >
>> > Applied to pci/host-designware for v3.15, thanks!
>>
>> - thanks
>>
>> >
>> > I update the summary to the following; let me know if it's not accurate:
>> >
>> > PCI: designware: Fix RC BAR to be single 64-bit non-prefetchable
>> > memory BAR
>>
>> - yes, it looks better
>>
>> Thanks,
>> Mohit
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/1] Designware:RC BARs setup related fix
@ 2014-02-21 0:59 Jingoo Han
0 siblings, 0 replies; 6+ messages in thread
From: Jingoo Han @ 2014-02-21 0:59 UTC (permalink / raw)
To: Mohit Kumar
Cc: Pratyush Anand, Arnd Bergmann, spear-devel@list.st.com,
linux-pci@vger.kernel.org, Jingoo Han
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^ permalink raw reply [flat|nested] 6+ messages in thread
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2014-02-19 12:04 [PATCH 1/1] Designware:RC BARs setup related fix Mohit Kumar
2014-02-19 21:53 ` Bjorn Helgaas
2014-02-20 4:13 ` Mohit KUMAR DCG
2014-02-20 6:45 ` Mohit KUMAR DCG
2014-02-20 19:26 ` Bjorn Helgaas
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